cnt64.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : cnt64.vhd
-- Design Date: Sep 14, 1998
-- Creation Date: Thu Jan 25 18:43:16 2001
-- Created By SpDE Version: SpDE 8.2 
-- Author: Randy Oyadomari, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description: This file contains macros and up counters used by
-- the the 64 deep FIFOs.
------------------------------------------------------------------------

package QL_PACKAGE_CNT64 is
   constant QL_LOGIC  : integer := 1;
   constant QL_BIDIR  : integer := 2;
   constant QL_INCELL : integer := 3;
   constant QL_CLOCK  : integer := 4;
   constant QL_HSCK   : integer := 5;
end QL_PACKAGE_CNT64;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity FRAG_A_CNT64 is
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
end FRAG_A_CNT64;


architecture BEHAVIORAL of FRAG_A_CNT64 is

	attribute ql_frag : integer;
	attribute ql_frag of BEHAVIORAL : architecture is 1;
begin 
 AZ <= A1 and (not A2) and A3 and (not A4) and A5 and (not A6) after 1 ns;

end BEHAVIORAL;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity AND2I0_CNT64 is
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end AND2I0_CNT64;


architecture SCHEMATIC of AND2I0_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_A_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   QL1 : FRAG_A_CNT64
      Port Map ( A1=>A, A2=>GND, A3=>B, A4=>GND, A5=>VCC, A6=>GND,
                 AZ=>Q_DUMMY );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity FRAG_M_CNT64 is
      Port (      B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                 NSS : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC );
end FRAG_M_CNT64;


architecture BEHAVIORAL of FRAG_M_CNT64 is

	attribute ql_frag : integer;
	attribute ql_frag of BEHAVIORAL : architecture is 1;
begin 
process (D1, D2, E1, E2, NSS, C1, C2, B1, B2, OS)
variable temp1, temp2, temp3 : std_logic;
begin 
   if (NSS = '1') then
       temp1 := E1 and not E2;
       temp2 := C1 and not C2;
   else
       temp1 := D1 and not D2; 
       temp2 := B1 and not B2; 
   end if; 
 
   if (OS = '1') then
       temp3 := temp1;
   else
       temp3 := temp2;
   end if;
 
   NZ <= temp1;
   OZ <= temp3;
end process;

end BEHAVIORAL;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity FRAG_Q_CNT64 is
      Port (      QC : In    STD_LOGIC;
                  QD : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  QZ : Out   STD_LOGIC );
end FRAG_Q_CNT64;


architecture BEHAVIORAL of FRAG_Q_CNT64 is

	attribute ql_frag : integer;
	attribute ql_frag of BEHAVIORAL : architecture is 1;
begin 
    process (QC, QR, QS)
    begin
       if QR = '1' then
          QZ <= '0';
       elsif QS = '1' then
          QZ <= '1';
       elsif QC = '1' and QC'EVENT then
          QZ <= QD; 
       end if;
    end process;

end BEHAVIORAL;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity FRAG_F_CNT64 is
      Port (      F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  FZ : Out   STD_LOGIC );
end FRAG_F_CNT64;


architecture BEHAVIORAL of FRAG_F_CNT64 is

	attribute ql_frag : integer;
	attribute ql_frag of BEHAVIORAL : architecture is 1;
begin 
 FZ <= F1 and (not F2) and F3 and (not F4) and F5 and (not F6) after 1 ns;

end BEHAVIORAL;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity DFFP_CNT64 is
      Port (     clk : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end DFFP_CNT64;


architecture SCHEMATIC of DFFP_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
   signal      N_1 : STD_LOGIC;
   signal      N_2 : STD_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
   signal      N_3 : STD_LOGIC;
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_F_CNT64
      Port (      F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  FZ : Out   STD_LOGIC );
   end component;

   component FRAG_A_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

   component FRAG_Q_CNT64
      Port (      QC : In    STD_LOGIC;
                  QD : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

   component FRAG_M_CNT64
      Port (      B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                 NSS : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   I_3 : FRAG_F_CNT64
      Port Map ( F1=>VCC, F2=>GND, F3=>VCC, F4=>GND, F5=>VCC, F6=>GND,
                 FZ=>N_1 );
   I_2 : FRAG_A_CNT64
      Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
                 AZ=>N_2 );
   I_1 : FRAG_Q_CNT64
      Port Map ( QC=>clk, QD=>N_3, QR=>GND, QS=>PRE, QZ=>Q_DUMMY );
   QL1 : FRAG_M_CNT64
      Port Map ( B1=>VCC, B2=>GND, C1=>VCC, C2=>GND, D1=>VCC, D2=>GND,
                 E1=>D, E2=>GND, NSS=>N_1, OS=>N_2, NZ=>open, OZ=>N_3 );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity NOR2I0_CNT64 is
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end NOR2I0_CNT64;


architecture SCHEMATIC of NOR2I0_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_A_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   QL1 : FRAG_A_CNT64
      Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>A, A5=>VCC, A6=>B,
                 AZ=>Q_DUMMY );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity DFFC_CNT64 is
      Port (     clk : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end DFFC_CNT64;


architecture SCHEMATIC of DFFC_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
   signal      N_1 : STD_LOGIC;
   signal      N_2 : STD_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
   signal      N_3 : STD_LOGIC;
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_F_CNT64
      Port (      F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  FZ : Out   STD_LOGIC );
   end component;

   component FRAG_A_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

   component FRAG_Q_CNT64
      Port (      QC : In    STD_LOGIC;
                  QD : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

   component FRAG_M_CNT64
      Port (      B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                 NSS : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   I_3 : FRAG_F_CNT64
      Port Map ( F1=>VCC, F2=>GND, F3=>VCC, F4=>GND, F5=>VCC, F6=>GND,
                 FZ=>N_1 );
   I_2 : FRAG_A_CNT64
      Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
                 AZ=>N_2 );
   I_1 : FRAG_Q_CNT64
      Port Map ( QC=>clk, QD=>N_3, QR=>CLR, QS=>GND, QZ=>Q_DUMMY );
   QL1 : FRAG_M_CNT64
      Port Map ( B1=>VCC, B2=>GND, C1=>VCC, C2=>GND, D1=>VCC, D2=>GND,
                 E1=>D, E2=>GND, NSS=>N_1, OS=>N_2, NZ=>open, OZ=>N_3 );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity AND2I2_CNT64 is
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end AND2I2_CNT64;


architecture SCHEMATIC of AND2I2_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_A_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   QL1 : FRAG_A_CNT64
      Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>A, A5=>VCC, A6=>B,
                 AZ=>Q_DUMMY );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity DFFPC_CNT64 is
      Port (     clk : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC;