cardbus_5632.prj

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

#-- Synplicity, Inc.
#-- Version 7.2.1      
#-- Project file D:\project\CardBus\Source\vhdl\cardbus_5632.prj
#-- Written on Wed Apr 07 21:23:30 2004


#add_file options
add_file -vhdl -lib work "D:/pasic/spde/data/ql5632-33/pci32_25um/pci32_25um.vhd"
add_file -vhdl -lib work "D:/pasic/spde/data/macros.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/R128X32_25UM.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/GCNTE5_0.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/RGEC5_1R.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/RGEC5_2.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/GCNTE5_2.vhd"
add_file -vhdl -lib work "dcount8.vhd"
add_file -vhdl -lib work "dcount16.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/GCNTE5_3.vhd"
add_file -vhdl -lib work "updcnt7_25um.vhd"
add_file -vhdl -lib work "ucnt7_25um.vhd"
add_file -vhdl -lib work "ram128x18_25um.vhd"
add_file -vhdl -lib work "ram128x9.vhd"
add_file -vhdl -lib work "r128a8.vhd"
add_file -vhdl -lib work "r128x4_25um.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/F128X4_25UM.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/CIS_DECODE.vhd"
add_file -vhdl -lib work "cfgtaddr_5632_280_pkg.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/CFGTADDR_CARDBUS.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/CARDBUS_WRAPPER.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/DMAREGRD.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/FIFOCONT.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/INITFLGS.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/DMACNTRL.vhd"
add_file -vhdl -lib work "D:/project/CardBus/Source/vhdl/cardbus_5632.vhd"
add_file -_pasic "D:/project/CardBus/Source/vhdl/cardbus_5632.sc"


#implementation: "vhdl"
impl -add vhdl

#device options
set_option -technology ECLIPSE
set_option -part ql5632-33
set_option -package pt280
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -fanout_limit 16
set_option -disable_io_insertion 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./CARDBUS_5632.qdf"

#implementation attributes
set_option -compiler_compatible ""
impl -active "vhdl"