cardbus_5632_modelsim.do

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

#------------------------------------------------------------------------------
#
# File : cardbus_5632 modelsim.do
# Last Modification: 06/26/2001
#
# Created In SpDE Version: SpDE 8.22
# Author :	Richard Yuan, QuickLogic Corporation
# Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
# this file for use in designing with QuickLogic devices only.
#	
# Description :
#	This script runs QL5632-33 vhdl reference design prelayout simulation 
#	in ModelSim.
#	 
# History:	
#	Date	        Author					Version
#	06/26/01		Richard Yuan			1.0
#		- Header added to conform to coding standard.
#       May/03/2002		Bernhard Andretzky		1.1
#		- adapded for 5632-33 reference design
#	11/18/02	Claire Pian Tu				1.2
#		- Added cmd_monitor test bench and wave signals
#
#------------------------------------------------------------------------------


# before running this script you should change your current directory
# in ModelSim to where the simulation files are by using the "cd" command

# cd c:/pasic/design/reference/pci5632_280/vhdl
cd d:/project/CardBus/Source/vhdl

# create work library
vlib work

# compile QuickLogic macros library
# you might need to add the drive letter to make it look like {c:/pasic/spde/...}
vcom -93 -work work {d:/pasic/spde/data/macros.vhd}

# compile QuickLogic RAM primitives
vcom -93 ram128x18_25um.vhd
vcom -93 ram128x9.vhd

# compile QL5432-33 PCI core simulation model files
vcom -93 -work work {d:/pasic/spde/data/ql5632-33/pci32_25um/v1_2/pci3233_25um.vhd}
vcom -93 -work work {d:/pasic/spde/data/ql5632-33/pci32_25um/pci32_25um.vhd}

# compile QL5432-33 reference design files
vcom -93 -work work r128x32_25um.vhd
vcom -93 -work work r128a8.vhd
vcom -93 -work work r128x4_25um.vhd
vcom -93 -work work ucnt7_25um.vhd
vcom -93 -work work updcnt7_25um.vhd
vcom -93 -work work cnt64.vhd
vcom -93 -work work lcnt64.vhd
vcom -93 -work work f128x4_25um.vhd
vcom -93 -work work dcount8.vhd
vcom -93 -work work dcount16.vhd
vcom -93 -work work gcnte5_0.vhd
vcom -93 -work work gcnte5_2.vhd
vcom -93 -work work gcnte5_3.vhd
vcom -93 -work work rgec5_1r.vhd
vcom -93 -work work rgec5_2.vhd
vcom -93 -work work cfgtaddr_5632_280_pkg.vhd
vcom -93 -work work cfgtaddr_cardbus.vhd
vcom -93 -work work cardbus_wrapper.vhd
vcom -93 -work work dmacntrl.vhd
vcom -93 -work work dmaregrd.vhd
vcom -93 -work work fifocont.vhd
vcom -93 -work work initflgs.vhd
vcom -93 -work work cardbus_5632.vhd

# compile test bench files
vcom -93 -work work utils_pkg.tb
vcom -93 -work work pci_pack.tb
vcom -93 -work work clk_gen.tb
vcom -93 -work work idt_fifo.tb
vcom -93 -work work pci_access.tb
vcom -93 -work work pci_arb.tb
vcom -93 -work work pci_mast.tb
vcom -93 -work work pci_tar.tb
vcom -93 -work work proto_chk.tb
vcom -93 -work work byte_enable_test.tb
vcom -93 -work work pci_cmd_test.tb
vcom -93 -work work pci_comp_5632.tb
vcom -93 -work work cmd_monitor.tb
vcom -93 -work work CIS.tb
vcom -93 -work work cardbus_wrapper_test.tb
#vcom -93 -work work cardbus_wrapper.tb
vcom -93 -work work cardbus_5632.tb

# start simulation
vsim -t 100ps work.t -wlf cardbus_5632.wlf
# open a waveform window
view wave
# add PCI signals
add wave /t/perrn
add wave /t/serrn
add wave /t/par
add wave /t/reqn
add wave /t/gntn
add wave /t/rstn
add wave /t/clk
add wave /t/idsel
add wave -format Literal -radix hexadecimal /t/ad(31:0)
add wave -format Literal -radix hexadecimal /t/cben(3:0)
add wave /t/framen
add wave /t/irdyn
add wave /t/devseln
add wave /t/trdyn
add wave /t/stopn

# add command Monitor signals
add wave /t/cmd_mon_1/pci_cmd 
add wave /t/cmd_mon_1/pci_cmd_l 
add wave /t/cmd_mon_1/config_add 
add wave -format Literal -radix hexadecimal /t/cmd_mon_1/mem_address

# run simulation till end
onbreak resume
run -all
#write transcript pci5632_280pre.doc
#quit -f