ucnt7_25um.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : ucnt7_25um.vhd
-- Design Date: June 9, 1998
-- Creation Date: Mon May 06 13:42:48 2002

-- Created By SpDE Version: SpDE 9.3 Alpha Build3
-- Author: Brian Faith, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description: This is the counter for generating the read
-- and write addresses in the FIFOs.
------------------------------------------------------------------------
-- This is the counter for generating the read adderss
-- and write addresses 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- inputs: enable,clk,rst
-- outputs: =q[6:0]=

entity ucnt7_25um is
   port (enable : in std_logic;
         clk : in std_logic;
         rst : in std_logic;
         q : out std_logic_vector (6 downto 0));
end ucnt7_25um;

architecture arch of ucnt7_25um is
signal q_reg : std_logic_vector (6 downto 0);

begin

q <= q_reg after 1 ns;

main : process (clk, rst)
begin
   if (rst = '1') then
      q_reg <= "0000000" after 1 ns;
   else if Rising_Edge(clk) then
      if (enable = '1') then
         q_reg <= q_reg + 1 after 1 ns;
      else
         q_reg <= q_reg after 1 ns;
      end if;
   else
      q_reg <= q_reg after 1 ns;
   end if;
end if;
end process main;

end arch;