rgec5_1r.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

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--
-- File : rgec5_1r.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	5-bit register with a reset value of 0.
--
-- Hierarchy:
--	This file represents the rgec5_1r block in f32a32.sch.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header added to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity rgec5_1r is port
	(
	CLK, CLR, EN: in std_logic;
	D: in std_logic_vector(4 downto 0);
	Q: out std_logic_vector(4 downto 0)
	);
end rgec5_1r;

architecture behavioral of rgec5_1r is

begin
	
	process (CLR, CLK)
	begin
		if CLR = '1' then Q <= "00000";
		elsif CLK'event and CLK = '1' then
			if EN = '1' then Q <= D; end if;
		end if;
	end process;

end behavioral;