clk_gen.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : clk_gen.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	Simulation models for the external programmable clock generator
--	on the PCI RDK board.
--	 
-- Hierarchy:
--	The clk_gen entity is to be used by pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--	06/26/01		Richard Yuan			1.0
--		- Header added to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;


entity clk_gen is
	port (s0,s1 : in std_logic;
		  lclk : out std_logic;
		  stop : in boolean 
		 );
end clk_gen;


architecture clk_gen_arch1 of clk_gen is
	constant skew : time := 7 ns;
	signal HalfCycleLocal : time := 10 ns;
	signal s1s0 : std_logic_vector(1 downto 0);
	signal lclk_int: std_logic;
begin


lclk <= lclk_int;

local_clock : process is begin
	lclk_int <= '0';
	wait for (skew + 1 ns);
	lclk_int <= '1';
	clk_gen_loop: loop
		wait for HalfCycleLocal;
		lclk_int <= not lclk_int;
		if (stop) then exit clk_gen_loop;
			end if;
		end loop;
	wait;
end process;


s1s0 <= (s1 & s0);

local_clock_speed : process (s1, s0) is begin
	case s1s0 is
		when "00" => HalfCycleLocal <= 35 ns; -- 14.318 MHz Base Clock
		when "0Z" => HalfCycleLocal <= 17 ns; -- 28.64 MHz
		when "01" => HalfCycleLocal <= 12 ns; -- 42.96 MHz
		when "Z0" => HalfCycleLocal <= 9 ns; -- 57.27 MHz
		when "ZZ" => HalfCycleLocal <= 7 ns; -- 71.59 MHz
		when "Z1" => HalfCycleLocal <= 6 ns; -- 85.91 MHz
		when "10" => HalfCycleLocal <= 5 ns; -- 100.2 MHz
		when "1Z" => HalfCycleLocal <= 4 ns; -- 114.6 MHz
		when "11" => HalfCycleLocal <= 12 ns; -- 229.1 MHz
		when others => HalfCycleLocal <= 10 ns;
	end case;
end process;

end clk_gen_arch1;