pci_tar.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

jptempvar8 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0010" )  ELSE '0';
jptempvar9 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0011" )  ELSE '0';
jptempvar10 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0110" )  ELSE '0';
jptempvar11 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0111" )  ELSE '0';
jptempvar12 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1100" )  ELSE '0';
jptempvar13 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1110" )  ELSE '0';
jptempvar14 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1111" )  ELSE '0';
jptempvar15 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0010" )  ELSE '0';
jptempvar16 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0011" )  ELSE '0';
jptempvar17 <=  '1' WHEN 
 BUS_SIZE = 64  ELSE '0';
jptempvar18 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  idle )  ELSE '0';
jptempvar19 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1101" )  ELSE '0';
jptempvar20 <=  '1' WHEN 
 ( x"00000000" & pci_ad(31 downto 0) )  >=  BASE_ADDRESS(63 downto 0)  ELSE '0';
jptempvar21 <=  '1' WHEN 
 ( x"00000000" & pci_ad(31 downto 0) )  <  std_logic_vector(unsigned(BASE_ADDRESS(63 downto 0)) + to_unsigned(MEM_SIZE,32))  ELSE '0';
jptempvar22 <=  '1' WHEN 
 (  pci_ad(31 downto 0) & lower_addr(31 downto 0)  )  >=  BASE_ADDRESS(63 downto 0)  ELSE '0';
jptempvar23 <=  '1' WHEN 
 (  pci_ad(31 downto 0) & lower_addr(31 downto 0)  )  <  ( std_logic_vector(unsigned(BASE_ADDRESS(63 downto 0)) + to_unsigned(MEM_SIZE,32))  )  ELSE '0';
jptempvar24 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  idle )  ELSE '0';
jptempvar25 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  dualaddress_cycle )  ELSE '0';
jptempvar26 <=  increment WHEN  ( req64_transaction )  = '1'  ELSE 4 ;
jptempvar27 <=  dataout_reg(63 downto 56) WHEN  (  NOT c_be_n(7) )  = '1'  ELSE  "10100101";
jptempvar28 <=  '1' WHEN 
 ( BUS_SIZE = 64 )  ELSE '0';
jptempvar29 <=  dataout_reg(55 downto 48) WHEN  (  NOT c_be_n(6) )  = '1'  ELSE  "10100101";
jptempvar30 <=  '1' WHEN 
 ( BUS_SIZE = 64 )  ELSE '0';
jptempvar31 <=  dataout_reg(47 downto 40) WHEN  (  NOT c_be_n(5) )  = '1'  ELSE  "10100101";
jptempvar32 <=  '1' WHEN 
 ( BUS_SIZE = 64 )  ELSE '0';
jptempvar33 <=  dataout_reg(39 downto 32) WHEN  (  NOT c_be_n(4) )  = '1'  ELSE  "10100101";
jptempvar34 <=  '1' WHEN 
 ( BUS_SIZE = 64 )  ELSE '0';
jptempvar35 <=  dataout_reg(31 downto 24) WHEN  (  NOT c_be_n(3) )  = '1'  ELSE  "10100101";
jptempvar36 <=  dataout_reg(23 downto 16) WHEN  (  NOT c_be_n(2) )  = '1'  ELSE  "10100101";
jptempvar37 <=  dataout_reg(15 downto  8) WHEN  (  NOT c_be_n(1) )  = '1'  ELSE  "10100101";
jptempvar38 <=  dataout_reg( 7 downto  0) WHEN  (  NOT c_be_n(0) )  = '1'  ELSE  "10100101";
jptempvar39 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  s_data )  ELSE '0';
jptempvar40 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  w_data )  ELSE '0';
jptempvar41 <=  '1' WHEN 
 ( target(7 downto 0) )  /=  (  idle )  ELSE '0';
jptempvar42 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  read_turnaround )  ELSE '0';
jptempvar43 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  read_turnaround )  ELSE '0';
jptempvar44 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  read_turnaround )  ELSE '0';
jptempvar45 <=  '1' WHEN 
 ( WaitStates =  0 )  ELSE '0';
jptempvar46 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  dualaddress_cycle )  ELSE '0';
jptempvar47 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  idle )  ELSE '0';
jptempvar48 <=   ( RANDOM_VAL MOD (MAX_WAITS - MIN_WAITS  +  1)) + MIN_WAITS WHEN VARIABLE_WAITS = '1' ELSE INITIAL_WAITS;
jptempvar49 <=  '1' WHEN 
 ( WaitStates = 0 )  ELSE '0';
jptempvar50 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  idle )  ELSE '0';
jptempvar51 <=   (RANDOM_VAL MOD (MAX_WAITS - MIN_WAITS  + 1))  +  MIN_WAITS WHEN  VARIABLE_WAITS = '1'  ELSE  SUBSEQUENT_WAITS;
jptempvar52 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  idle )  ELSE '0';
jptempvar53 <=  WaitStates - 1 WHEN  ( jptempvar54 = '1' )  ELSE 0;
jptempvar54 <=  '1' WHEN 
 ( WaitStates >  0 )  ELSE '0';
jptempvar55 <=  StopWaits -  1 WHEN  ( jptempvar56 = '1' )  ELSE  0;
jptempvar56 <=  '1' WHEN 
 ( StopWaits >  0 )  ELSE '0';
jptempvar57 <=  '1' WHEN 
 ( BUS_SIZE = 64 )  ELSE '0';
jptempvar58 <=  '1' WHEN 
 ( target(7 downto 0) )  =  (  idle )  ELSE '0';
jptempvar59 <=  '1' WHEN 
 ( STOP_COUNT <= data_count)  ELSE '0';
jptempvar60 <=  '1' WHEN 
 ( StopWaits <= 1 )  ELSE '0';
jptempvar61 <=  '1' WHEN 
 ( STOP_COUNT = data_count +  1 )  ELSE '0';
jptempvar62 <=  '1' WHEN 
 ( STOP_WAITS =  0)  ELSE '0';
jptempvar63 <=  '1' WHEN 
 ( retry_count_counter = 0 )  ELSE '0';
jptempvar64 <=  '1' WHEN  ( retry_count_counter = 0 )  ELSE '0';

--Beginning of actual code
  ADDRESS_64 <= jptempvar0;

  frame <=  NOT frame_n;
  irdy <=  NOT irdy_n;
  trdy <=  NOT trdy_n;
  devsel <=  NOT devsel_n;
  req64 <=  NOT req64_n;
  rst <=  NOT rst_n;
  stop <=  NOT stop_n;
 

--ALWAYS: posedge clk or posedge rst) begin if (rst)         target <= idle
target_state: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
         target(7 downto 0) <=  idle;
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
CASE target(7 downto 0) IS
  WHEN idle =>
IF  ( TARGET_ABORT )  = '1'  THEN
                          target(7 downto 0) <=  aborting;
  ELSIF  (  ( frame )  AND  (  ADDRESS_64 AND   ( jptempvar1 )  )  )  = '1'  THEN
                         target(7 downto 0) <=  dualaddress_cycle;
  ELSIF  (  ( frame )  AND  (   (  NOT ADDRESS_64 )  AND   ( jptempvar2 )  )  )  = '1'  THEN
                         target(7 downto 0) <=  wait_cycle;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar3 )  )  )  = '1'  THEN
    target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar4 )  )  )  = '1'  THEN
    target(7 downto 0) <=  w_data;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar5 )  )  )  = '1'  THEN
    target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar6 )  )  )  = '1'  THEN
    target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar7 )  )  )  = '1'  THEN
    target(7 downto 0) <=  w_data;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar8 )  )  )  = '1'  THEN
                         target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match AND   ( jptempvar9 )  )  )  = '1'  THEN
                         target(7 downto 0) <=  w_data;
  ELSE target(7 downto 0) <=  idle;
 END IF;
  WHEN dualaddress_cycle =>
IF  (  ( frame )  AND  (  match64 AND   ( jptempvar10 )  )  )  = '1'  THEN
    target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match64 AND   ( jptempvar11 )  )  )  = '1'  THEN
    target(7 downto 0) <=  w_data;
  ELSIF  (  ( frame )  AND  (  match64 AND   ( jptempvar12 )  )  )  = '1'  THEN
    target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match64 AND   ( jptempvar13 )  )  )  = '1'  THEN
    target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match64 AND   ( jptempvar14 )  )  )  = '1'  THEN
    target(7 downto 0) <=  w_data;
  ELSIF  (  ( frame )  AND  (  match64 AND   ( jptempvar15 )  )  )  = '1'  THEN
                         target(7 downto 0) <=  read_turnaround;
  ELSIF  (  ( frame )  AND  (  match64 AND   ( jptempvar16 )  )  )  = '1'  THEN
                         target(7 downto 0) <=  w_data;
  ELSE target(7 downto 0) <=  idle;
 END IF;
  WHEN read_turnaround =>
                      target(7 downto 0) <=  s_data;
 
 WHEN s_data =>
IF  (  NOT  (  ( trdy_reg OR  stop )  AND  irdy )  )  = '1'  THEN
                     target(7 downto 0) <=  s_data;
  ELSIF  (  ( irdy )  AND  (   ( trdy_reg OR  stop )  AND  (  NOT frame )  )  )  = '1'  THEN
                      target(7 downto 0) <=  idle;
  ELSIF  (  ( irdy )  AND  (   ( trdy_reg OR  stop )  AND  frame )  )  = '1'  THEN
                      target(7 downto 0) <=  s_data;
  END IF;
 WHEN w_data =>
IF  (  NOT  (  ( trdy_reg OR  stop )  AND  irdy )  )  = '1'  THEN
       target(7 downto 0) <=  w_data;
  ELSIF  (  ( irdy )  AND  (   ( trdy_reg OR  stop )  AND  (  NOT frame )  )  )  = '1'  THEN
                      target(7 downto 0) <=  idle;
  ELSIF  (  ( irdy )  AND  (   ( trdy_reg OR  stop )  AND  frame )  )  = '1'  THEN
                      target(7 downto 0) <=  w_data;
  END IF;
 WHEN wait_cycle =>
target(7 downto 0) <=  idle;
  WHEN aborting =>
IF  (  NOT TARGET_ABORT )  = '1'  THEN
 target(7 downto 0) <=  idle;
                   ELSIF  ( Assert_Target_Abort )  = '1'  THEN
 target(7 downto 0) <=  idle;
  END IF;
 WHEN others =>
target(7 downto 0) <=  idle;
  END CASE;
 END IF;
 END PROCESS;

ack64_n <=   (  NOT ack64 ) after OUTPUT_DELAY WHEN  ( ack64_oe )  = '1'  ELSE   ( 'Z' ) after OUTPUT_DELAY;
  ack64 <= devsel AND  req64_transaction;
  ack64_oe <= adoe OR  write_trdy_en;
 

--ALWAYS: posedge clk or posedge rst) begin if (rst)     req64_transaction <= 1'b0
check_req64:PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
     req64_transaction <=  '0';
      --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
  IF  (  (  ( jptempvar17 )  )  AND  (   ( req64 OR  req64_transaction )  AND   (  (  NOT  ( jptempvar18 )  )  OR  frame )  )  )  = '1'  THEN
    req64_transaction <=  '1';
  ELSE
    req64_transaction <=  '0';
 END IF;
 END IF;
  END PROCESS;



--ALWAYS: posedge clk or posedge rst) begin if (rst)     lower_addr <= 32'b0
set_lower: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
     lower_addr(31 downto 0) <=  "00000000000000000000000000000000";
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
     IF  ( jptempvar19 )  = '1'  THEN
        lower_addr(31 downto 0) <=  pci_ad(31 downto 0);
     ELSE
        lower_addr(31 downto 0) <=  lower_addr(31 downto 0);
     END IF;
 END IF;
  END PROCESS;

match <=   (  ( jptempvar20 )  AND   ( jptempvar21 )  )  WHEN  ( frame )  = '1'  ELSE  '0';
match64 <=   (  ( jptempvar22 )  AND   ( jptempvar23 )  )  WHEN  ( frame )  = '1'  ELSE  '0';
increment<= 8 WHEN (BUS_SIZE = 64) ELSE 4;
 

--ALWAYS: posedge clk or posedge rst) begin if (rst)         mem_addr <= 64'h0
set_mem_addr: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
         mem_addr <=  BASE_ADDRESS;
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
  IF  ( match AND   ( jptempvar24 )  )  = '1'  THEN
         mem_addr <=   "00000000000000000000000000000000" & pci_ad(31 downto 0) ;
  ELSIF  ( match64 AND   ( jptempvar25 )  )  = '1'  THEN
         mem_addr <=   pci_ad(31 downto 0) & lower_addr(31 downto 0) ;
  ELSIF  ( trdy_reg AND  irdy )  = '1'  THEN
          mem_addr <=  std_logic_vector(unsigned(mem_addr) + to_unsigned(jptempvar26,4)) ;
  ELSE
          mem_addr <=  mem_addr;
 END IF;
 END IF;
  END PROCESS;

-----THIS SHOULD BE OK.  mem_addr changes on the clock edge, and then is used
-----below on a clock edge.  The one clock delay is still present with these
----- added variables
addr_diff <= std_logic_vector(unsigned(mem_addr(63 downto 0)) - unsigned(BASE_ADDRESS(31 downto 0)));
----addr_diff should ALWAYS have the 63 downto 31 being zero, so this works
check_addr <= to_integer(unsigned(addr_diff(30 downto 0)));
curr_addr <= 0 when check_addr >= MEM_SIZE else check_addr;

dataout_reg(63 downto 0) <=  MyMemory(curr_addr+7) & --THIS IS CONCATENATION
MyMemory(curr_addr+6) & --THIS IS CONCATENATION
MyMemory(curr_addr+5) & --THIS IS CONCATENATION
MyMemory(curr_addr+4) & --THIS IS CONCATENATION
MyMemory(curr_addr+3) & --THIS IS CONCATENATION
MyMemory(curr_addr+2) & --THIS IS CONCATENATION
MyMemory(curr_addr+1) & --THIS IS CONCATENATION
MyMemory(curr_addr);

memcheck(63 downto 0) <=  MyMemory(7) & --THIS IS CONCATENATION
MyMemory(6) & --THIS IS CONCATENATION
MyMemory(5) & --THIS IS CONCATENATION
MyMemory(4) & --THIS IS CONCATENATION
MyMemory(3) & --THIS IS CONCATENATION
MyMemory(2) & --THIS IS CONCATENATION
MyMemory(1) & --THIS IS CONCATENATION
MyMemory(0);

  pci_ad(63 downto 56) <=   ( jptempvar27 ) after OUTPUT_DELAY WHEN  (  (  (  ( jptempvar28 )  AND  ack64 )  AND  adoe )  )  = '1'  ELSE  "ZZZZZZZZ" after OUTPUT_DELAY;
  pci_ad(55 downto 48) <=   ( jptempvar29 ) after OUTPUT_DELAY WHEN  (  (  (  ( jptempvar30 )  AND  ack64 )  AND  adoe )  )  = '1'  ELSE  "ZZZZZZZZ" after OUTPUT_DELAY;
  pci_ad(47 downto 40) <=   ( jptempvar31 ) after OUTPUT_DELAY WHEN  (  (  (  ( jptempvar32 )  AND  ack64 )  AND  adoe )  )  = '1'  ELSE  "ZZZZZZZZ" after OUTPUT_DELAY;
  pci_ad(39 downto 32) <=   ( jptempvar33 ) after OUTPUT_DELAY WHEN  (  (  (  ( jptempvar34 )  AND  ack64 )  AND  adoe )  )  = '1'  ELSE  "ZZZZZZZZ" after OUTPUT_DELAY;