cardbus_5632.qcf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

#QuickLogic Constraint file
#Automatically generated by SpDE version SpDE 9.5.4 Internal Build1
#Date: 4/7/2004 at 23:29


#-*-*-*- ************************************************* -*-*-*-

#-*-*-*-        DO NOT MANUALLY EDIT BELOW THIS LINE       -*-*-*-

#-*-*-*- ************************************************* -*-*-*-

#[Part Name]
partname ql5632-33


#[Package Name]
packname PT280


#[Path constraints from the Path Analyzer]


#[Fixed Pin Placement]


#[Fixed FF Placement]


#[Fixed Ram Placement]


#[Fixed ECU Placement]


#[Pull FF]


#[Duplication constraints]


#[False Path Constraints]


#[Multi-Cycle Path Constraints]


#[Clock Constraints]


#[Frequency Constraints]


#[Point To Point Constraints]


#[Unused pads tie-off]
UnusedIO GND


#[Pin Standards ]


#[IOBank Standards]


#[IO SlewRate]


#[module name and window size for Window based placer]


#[routing priority for net(s)]
# Routing Priority for nets greater than 0 are only printed
# 0 -> Normal, 1 -> High, 2 -> Very High