📄 cardbus_wrapper_test.tb
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--
-- File : cardbus_wrapper.tb
-- Last Modification: 2/11/2004
--
-- Created In SpDE Version: SpDE 9.5.3
-- Author : Claire Pian Tu, QuickLogic Corporation
-- Copyright (C) 2003, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--
-- Description :
-- Procedures that are used to test the cardbus_wrapper module
--
-- Hierarchy:
-- This file provides a package to be used in pci5(6/7)32_280.tb.
--
-- History:
-- Date Author Version
-- 02/11/04 Claire Pian Tu 1.0
-- - Initial
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
use work.pci_pack.all;
use work.pci_access_package.all;
package cardbus_wrapper_test_package is
procedure cstschg_test (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal tb_CSTSCHG : in std_logic;
signal tb_wp : out std_logic;
signal tb_ready : out std_logic;
signal tb_bvd : out std_logic_vector(2 downto 1);
signal tb_gwake : out std_logic;
signal tb_intr : out std_logic;
signal passed : out integer
);
procedure cint_test (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal tb_intr: out std_logic;
signal tb_CINT_n : in std_logic;
signal passed : out integer
);
procedure caudio_test( --inputs to the procedure
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal tb_CAUDIO: in std_logic;
signal tb_BAM : out std_logic;
signal tb_PWM : out std_logic ;
signal passed : out integer
);
procedure cclkrun_test( --inputs to the procedure
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal tb_CCLKRUN_n : inout std_logic;
signal tb_clk_resume : out std_logic;
signal tb_clk_stopped : in std_logic ;
signal passed : out integer
);
procedure cis_readback_test (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal passed : out integer
);
constant FcnEventReg_Addr : std_logic_vector(63 downto 0) := x"00000000CB000300";
constant FcnMaskReg_Addr : std_logic_vector(63 downto 0) := x"00000000CB000304";
constant FcnStateReg_Addr : std_logic_vector(63 downto 0) := x"00000000CB000308";
constant FcnForceReg_Addr : std_logic_vector(63 downto 0) := x"00000000CB00030C";
constant CardBus_Bar : std_logic_vector(63 downto 0) := x"00000000CB000000";
shared variable addr : std_logic_vector(31 downto 0);
shared variable data : std_logic_vector(31 downto 0);
shared variable outline : line;
shared variable i,j : integer;
end cardbus_wrapper_test_package;
package body cardbus_wrapper_test_package is
procedure cstschg_test (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal tb_CSTSCHG : in std_logic;
signal tb_wp : out std_logic;
signal tb_ready : out std_logic;
signal tb_bvd : out std_logic_vector(2 downto 1);
signal tb_gwake : out std_logic;
signal tb_intr : out std_logic;
signal passed : out integer
) is
variable k : integer;
begin
i := 0;
j := 0;
k := 0;
write(outline, string'("["));
write(outline, now);
write(outline, string'("] START OF CSTSCHG TEST"));
writeline(output, outline);
write(outline, string'("Reading default values of all CSTSCHG-related registers"));
writeline(output, outline);
-- set variables back to inactive state
tb_wp <= '0'; -- bit 0
tb_ready <= '0'; -- bit 1
tb_bvd(2) <= '0'; -- bit 2
tb_bvd(1) <= '0'; -- bit 3
tb_gwake <= '0'; -- bit 4
tb_intr <= '0'; -- bit 15
-- read event register
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
data_array(0) <= x"00000000";
data_array(1) <= x"00000000";
data_array(2) <= x"00000000";
data_array(3) <= x"00000000";
-- clear event notice
address_reg <= FcnEventReg_Addr;
pci_access(address_reg,data_reg,MEM_READ,x"FF",4,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
master1_quiet,be_array,data_array,CLK);
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Enabling all event sources for CSTSCHG generation."));
writeline(output, outline);
address_reg <= FcnMaskReg_Addr;
data_reg <= x"FFFFFFFFFFFFFFFF";
pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
master1_quiet,be_array,data_array,CLK);
-- ctu CSTSCHG TEST #1
-- change first 3 bits to 1, status changed should assert
-- present state should also be asserted
write(outline, string'("Toggling state inputs..."));
writeline(output, outline);
tb_wp <= '1'; -- bit 0
tb_ready <= '1'; -- bit 1
tb_bvd(2) <= '1'; -- bit 2
tb_bvd(1) <= '0'; -- bit 3
tb_gwake <= '0'; -- bit 4
tb_intr <= '0'; -- bit 15
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