cardbus_5632aldec_post.do

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

#------------------------------------------------------------------------------
#
# File : cardbus_5632aldec_post.do
# Last Modification: 05/04/2004
#
# Created In SpDE Version: SpDE 9.3
# Author : Bernhard Andretzky, QuickLogic Corporation
# Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
# this file for use in designing with QuickLogic devices only.
#	
# Description :
#	This script runs QL5632-33 vhdl reference design postlayout simulation 
#	in Active-HDL 5.1
#	 
# History:	
#	Date	        Author					Version
#	06/26/01	Bernhard Andretzky			1.0
#	07/25/02	Jens Niemann				1.1
#		- Some variables defined to change all device and 
#		  package in one block
#	11/18/02	Claire Pian Tu				1.2
#		- Added cmd_monitor test bench and wave signals
#	05/04/04	Claire Pian Tu				1.3
#		- Modified for CardBus IP
#------------------------------------------------------------------------------

#--------Instructions, that can be used with Aldec Macro Language------------
# cd ..  for going one level down
# cd directoryname for going one level up
# pwd for checking current directory
# alternatively you can use the old DOS instruction with adding an 
# exclamation mark
# e.g.  !dir *.vhd
# $dsn means the directory in which the do file is

# XXXXXXXXXXXXXXXXXX Design setting section XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

# Change this path to your source file directory
#set curpath c:\pasic\design\reference\pci5632_280\vhdl
set curpath d:\project\CardBus\Source\vhdl

#set primitivepath c:\pasic\spde\data
set primitivepath d:\pasic\spde\data

set design_name cardbus_5632post

set adf_file_name cardbus_5632post.adf 

set vhq_file cardbus_5632.vhq

set cfg_comp_tb pci_comp_5632.tb
set top_level_tb cardbus_5632.tb

#set sdf_file c:\pasic\design\pci5632_280\vhdl\pci5632_280.sdf
set sdf_file d:\project\CardBus\Source\vhdl\cardbus_5632.sdf

set sdf_target /cardbus_5632_1
# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

# create a new design in the current directory in Active-HDL and open it

createdesign $design_name $curpath
opendesign $adf_file_name
# create work library
alib work


# create the qlprims library to store the primitives
# if you installed QuickLogic-specific libraries during Aldec installation,
#   it has already been created and you will get a message which is fine
alib qlprims
# if it was installed during Aldec installation, it is defaulted to read-only
# need to change it to read/write in order to update it
setlibrarymode -rw qlprims

# compile QuickLogic post-layout primitives
# you might need to add the drive letter to make it look like c:/pasic/spde/...

addfile -vhdl $primitivepath/qlvtl95.vhd
acom -work qlprims -accept87 $primitivepath/qlvtl95.vhd

# compile the postlayout netlist and add the sdf file
addfile -vhdl $curpath/$vhq_file
acom $curpath/$vhq_file


# compile test bench files
addfile -vhdl $curpath/utils_pkg.tb
acom $curpath/utils_pkg.tb
addfile -vhdl $curpath/clk_gen.tb
acom $curpath/clk_gen.tb
addfile -vhdl $curpath/idt_fifo.tb
acom $curpath/idt_fifo.tb
addfile -vhdl $curpath/pci_pack.tb
acom $curpath/pci_pack.tb
addfile -vhdl $curpath/pci_access.tb
acom $curpath/pci_access.tb
addfile -vhdl $curpath/pci_arb.tb
acom $curpath/pci_arb.tb
addfile -vhdl $curpath/pci_mast.tb
acom $curpath/pci_mast.tb
addfile -vhdl $curpath/pci_tar.tb
acom $curpath/pci_tar.tb
# file used in protocol checking
# this file must be copied to the local src directory (which is the -c)
addfile -c -txt $curpath/bus_chk.mem
addfile -vhdl $curpath/proto_chk.tb
acom $curpath/proto_chk.tb
addfile -vhdl $curpath/byte_enable_test.tb
acom $curpath/byte_enable_test.tb
addfile -vhdl $curpath/pci_cmd_test.tb
acom $curpath/pci_cmd_test.tb
addfile -vhdl $curpath/$cfg_comp_tb
acom $curpath/$cfg_comp_tb
addfile -vhdl $curpath/cmd_monitor.tb
acom $curpath/cmd_monitor.tb
addfile -vhdl $curpath/CIS.tb
acom $curpath/CIS.tb
addfile -vhdl $curpath/cardbus_wrapper_test.tb
acom $curpath/cardbus_wrapper_test.tb
addfile -vhdl $curpath/$top_level_tb
acom $curpath/$top_level_tb

# add the sdf file
addfile -sdf $sdf_file

# start simulation with worst-case timing and 100ps resolution
asim -sdfmax $sdf_target =$sdf_file -t 100ps t t_arch
# open a waveform window
view wave
# add PCI signals
wave perrn
wave serrn
wave par
wave reqn
wave gntn
wave rstn
wave clk
wave idsel
wave -literal -hex ad
wave -literal -hex cben
wave framen
wave irdyn
wave devseln
wave trdyn
wave stopn

#cmd_monitor signals
wave -literal -hex cmd_mon_1/mem_address
wave cmd_mon_1/PCI_CMD
wave cmd_mon_1/PCI_CMD_l
wave cmd_mon_1/config_add

# run simulation till end
run -all