cis.tb

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TB 代码 · 共 52 行

--------------------------------------------------------------------------------
--
-- File : CIS.tb
-- Last Modification: 03/22/2003
--
-- Created In SpDE Version: SpDE 9.5.3
-- Author :	Claire Pian Tu, QuickLogic Corporation
-- Copyright (C) 2004, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	CIS ROM simulation model.  
--	This is part of the test bench suite.
--
-- Hierarchy:
--	The CIS entity is to be used in cardbus_5632.tb.
--
-- History:	
--	Date	        Author					Version
--  03/22/04		Claire Pian Tu			1.0
--		- Initial release.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity CIS is
	port (
		pad_CIS_ADR : in std_logic_vector(9 downto 2);
		pad_CIS_data : out std_logic_vector(31 downto 0)
		);
end CIS;

architecture CIS_arch of CIS is
begin
	CIS : process(pad_CIS_ADR) is begin
		if pad_CIS_ADR(9 downto 8) = "00" then
			case pad_CIS_ADR(3 downto 2) is
				when "00" => pad_CIS_data <= x"04030201";
				when "01" => pad_CIS_data <= x"08070605";
				when "10" => pad_CIS_data <= x"0C0B0A09";
				when "11" => pad_CIS_data <= x"100F0E0D";
				when others => pad_CIS_data <= x"00000000";
			end case;
		else
			pad_CIS_data <= x"00000000";
		end if;
	end process;
end CIS_arch;