cis_decode.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

-----------------------------------------------------------------------
--	  File : CIS_decode.vhd
--   
--    DESCRIPTION: 
--			This file decodes the User address and flags the user design if
--			CIS data is accessed.
--
--    HIERARCHY:  
--			 This file is used in the top-level design as part of user design
--
--    AUTHOR: Claire Pian Tu
--
--    HISTORY: 
--    Date	        Author					Version
--    02/04/04		Claire Pian Tu			1.0
--		- Initial release, --		
-- Copyright (C) 2004, Licensed Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
--
-- IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
-- This design is provided without warranty of any kind.
-- QuickLogic Corporation does not warrant, guarantee or make any representations
-- regarding the use, or the results of the use, of this design. QuickLogic
-- disclaims all implied warranties, including but not limited to implied
-- warranties of merchantability and fitness for a particular purpose. In addition
-- and without limiting the generality of the foregoing, QuickLogic does not make
-- any warranty of any kind that any item developed based on this design, or any
-- portion of it, will not infringe any copyright, patent, trade secret or other
-- intellectual property right of any person or entity in any country. It is the
-- responsibility of the user of the design to seek licenses for such intellectual
-- property rights where applicable. QuickLogic shall not be liable for any
-- damages arising out of or in connection with the use of the design including
-- liability for lost profit, business interruption, or any other damages whatsoever.
--
-----------------------------------------------------------------------*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity CIS_decode is

port (
	-- outputs
	CIS_Hit:	out std_logic;
	-- inputs
	clk:		in std_logic;
	reset:		in std_logic;
	BAR_match:	in std_logic;
	addr_phase:	in std_logic;
    last_cycle: in std_logic;
	user_addr:	in std_logic_vector(9 downto 4)
	);
end CIS_decode;

architecture behavioral of CIS_decode is
begin
	-- CIS address decode
	-- CT added this portion for generating CIS_Hit
	process (clk, reset)
	begin
		if reset = '1' then
			CIS_Hit <= '0';
		elsif clk'event and clk = '1' then
			if (BAR_match = '1' and addr_phase = '1' and user_addr(9 downto 4) = "000000") then
				CIS_Hit <= '1';
	        elsif last_cycle = '1' then
				CIS_Hit <= '0';
	        end if;
		end if;
	end process;

end behavioral;