utils_pkg.tb

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TB 代码 · 共 581 行 · 第 1/2 页

      -- assign the string
		while ntmp > 0 loop
      	case ntmp rem 10 is
         	when 0 => stmp(index) := '0';
         	when 1 => stmp(index) := '1';
         	when 2 => stmp(index) := '2';
         	when 3 => stmp(index) := '3';
         	when 4 => stmp(index) := '4';
         	when 5 => stmp(index) := '5';
         	when 6 => stmp(index) := '6';
         	when 7 => stmp(index) := '7';
         	when 8 => stmp(index) := '8';
         	when 9 => stmp(index) := '9';
         	when others =>
            	assert(false)
            	report "[int2str]  You've got a serious problem!!!"
            	severity failure;
      	end case;
         ntmp := ntmp /10;
         index := index + 1;
   	end loop;
      return stmp((index-1) downto 1);
   end if;
end;


-- boolean to string
function bool2str(bool : boolean) return string is
begin
   if bool then
      return ("TRUE");
   else
      return("FALSE");
   end if;
end;


-- vector to binary string
function vec2bstr(vec: std_logic_vector; size : natural) return string is
variable	stmp: string(size downto 1) := (others => '0');
variable	j: integer;
begin
   for i in 1 to size loop
      case vec(i + vec'low -1) is
         when '0' => stmp(i) := '0';
         when '1' => stmp(i) := '1';
         when 'U' => stmp(i) := 'U';
         when 'X' => stmp(i) := 'X';
         when 'Z' => stmp(i) := 'Z';
         when 'W' => stmp(i) := 'W';
         when 'L' => stmp(i) := 'L';
         when 'H' => stmp(i) := 'H';
         when '-' => stmp(i) := '-';
      end case;
      assert((stmp(i) = '0') or (stmp(i) = '1'))
      report "[vec2bstr]  Trying to convert non-bit value!"
      severity warning;
   end loop;
   return stmp;
end;


-- vector to hex string
function vec2hstr(vec: std_logic_vector; size : natural) return string is
variable	stmp: string((size+1) downto 1) := (others => '0');
variable vtmp4 : std_logic_vector(3 downto 0);
variable vtmp3 : std_logic_vector(2 downto 0);
variable vtmp2 : std_logic_vector(1 downto 0);
variable temp : std_logic_vector(3 downto 0);
variable i : integer;
variable j : integer;
variable tmp_vec : std_logic_vector((vec'length - 1) downto 0);
begin
	-- need to invert vec if defined as "std_logic_vector(m to n)"
	if vec'left < vec'right then
		i := 0;
		for j in vec'right downto vec'left loop
			tmp_vec(i) := vec(j);
			i := i + 1;
		end loop;
	else
		tmp_vec := vec;
	end if;

   stmp(1) := 'H';
   i := 2;
   j := 0;

	while i <= (size +1) loop
      if (j + 3) <= tmp_vec'high then
			temp := tmp_vec(3 downto 0);
			vtmp4 := tmp_vec((j+3) downto j);
			case vtmp4 is
            when "0000" => stmp(i) := '0';
            when "0001" => stmp(i) := '1';
            when "0010" => stmp(i) := '2';
            when "0011" => stmp(i) := '3';
            when "0100" => stmp(i) := '4';
            when "0101" => stmp(i) := '5';
            when "0110" => stmp(i) := '6';
            when "0111" => stmp(i) := '7';
            when "1000" => stmp(i) := '8';
            when "1001" => stmp(i) := '9';
            when "1010" => stmp(i) := 'A';
            when "1011" => stmp(i) := 'B';
            when "1100" => stmp(i) := 'C';
            when "1101" => stmp(i) := 'D';
            when "1110" => stmp(i) := 'E';
            when "1111" => stmp(i) := 'F';
            when others =>
					stmp(i) := '?';
               assert false
               report "[vec2hstr]  Trying to convert non-bit value!"
               severity warning;
         end case;
         if j + 4 <= (tmp_vec'high + 1) then
      		j := j + 4;
         end if;
      elsif (j + 2) = tmp_vec'high then
			vtmp3 := tmp_vec((j + 2) downto j);
			case vtmp3 is
				when "000" => stmp(i) := '0';
				when "001" => stmp(i) := '1';
				when "010" => stmp(i) := '2';
				when "011" => stmp(i) := '3';
				when "100" => stmp(i) := '4';
				when "101" => stmp(i) := '5';
				when "110" => stmp(i) := '6';
				when "111" => stmp(i) := '7';
				when others =>
					stmp(i) := '?';
               assert false
               report "[vec2hstr]  Trying to convert non-bit value!"
               severity warning;
			end case;
         j := j + 3;
      elsif (j + 1) = tmp_vec'high then
			vtmp2 := tmp_vec((j + 1) downto j);
			case vtmp2 is
				when "00" => stmp(i) := '0';
				when "01" => stmp(i) := '1';
				when "10" => stmp(i) := '2';
				when "11" => stmp(i) := '3';
				when others =>
					stmp(i) := '?';
               assert false
               report "[vec2hstr]  Trying to convert non-bit value!"
               severity warning;
			end case;
         j := j + 2;
      elsif(j = tmp_vec'high) then
			case tmp_vec(j) is
				when '0' => stmp(i) := '0';
				when '1' => stmp(i) := '1';
				when others =>
					stmp(i) := '?';
               assert false
               report "[vec2hstr]  Trying to convert non-bit value!"
               severity warning;
         end case;
         j := j + 1;
      end if;
      i := i + 1;
   end loop;
	return stmp;
end;


-- string to bit vector
function str2vec(str : string) return bit_vector is
variable tmp : bit_vector(str'range);
begin
	for i in str'range loop
		if str(i) = '1' then
			tmp(i) := '1';
		elsif str(i) = '0' then
			tmp(i) := '0';
      else
         tmp(i) := '0';
         assert false
         report "[str2vec]  Trying to convert non-bit value!"
         severity warning;
		end if;
	end loop;
	return tmp;
end;


-- bit check
function IsBit(sig : std_logic) return boolean is
begin
	if sig = '1' or sig = '0' then
		return true;
	else
		return false;
	end if;
end IsBit;


-- convert bit to boolean
function bit2bool(bit : std_logic) return boolean is
begin
   if bit = '1' then
      return(true);
   else
      return(false);
   end if;
end;

-- convert active high bit to boolean
-- -> accurately assesses '1'
function HiBit2Bool(bit : std_logic) return boolean is
begin
   if bit = '1' then
      return(true);
   else
      return(false);
   end if;
end;

-- convert active high bit to boolean
-- -> accurately assesses '0'
function LoBit2Bool(bit : std_logic) return boolean is
begin
   if bit = '0' then
      return(false);
   else
      return(true);
   end if;
end;



-- convert bit to string
function bit2str(bit : std_logic) return string is
variable ret_str : string(1 downto 1);
begin
   if bit = '1' then
      ret_str :="1";
   elsif bit = '0' then
      ret_str :="0";
   else
      ret_str :="?";
      assert false
      report "[bit2str]  Trying to convert non-bit value!"
      severity warning;
   end if;
   return(ret_str);
end;



  -- RANDOM generates a random number with uniform distribution between 0 and 1.
  -- This function uses the multiplicative congruential method, using
  -- the following algorithm:
  --       X(n+1) = A[X(n) + C] mod M
  --       R(n) = X(n)/M
  -- where
  --       M = 2**d, such that M(M-1) is close to 2**32 -1
  --       C = 0
  --       A = 8t +- 3, such that t is a positive integer and A
  --                                            is close to 2**(d/2)
  --       Seed(n) is a random number between 0 and M-1, with period M/4
  --       Seed(0) is the seed for the sequence; must be the real representation
  --            of an odd positive integer.
  --       X(n) is a random number between 0 and 1
  --
  procedure RANDOM(variable Seed: inout real; variable X: out real) is
    variable M: integer := 32768;
    variable A: integer := 12869;
    variable iSeed: integer := integer(Seed);
    variable iTemp: integer;
  begin
    if Seed <= 0.0 then
      assert false report "Seed <= 0 in RANDOM(Seed, X)" severity WARNING;
      Seed := 1.0;
      X := 0.0;
    else
      iTemp := iSeed*A;
      iSeed := iTemp/M;
      iSeed := iTemp - iSeed*M;
      Seed := real(iSeed);
      X := Seed/real(M);
    end if;
  end RANDOM;

-------------------------------------------------------------------------------
end utils_pkg;          -- End of Package Body
-------------------------------------------------------------------------------