dcount16.vhd

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· VHDL 代码 · 共 91 行

--------------------------------------------------------------------------------
--
-- File : dcount16.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed Customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This file implements an 16-bit down counter converted from schematic.
--	 
-- Hierarchy:
--	The dcount16 entity is to be used in dmacntrl.vhd.
--
-- History:	
--	Date	        Author					Version
--	06/26/01		Richard Yuan			1.0
--		- Header added to conform to coding standard.
--
--------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity dcount16 is
      Port (     CLR : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                 CLK : In    STD_LOGIC;
                LOAD : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR (15 downto 0);
                   Q : Out   STD_LOGIC_VECTOR (15 downto 0) );
end dcount16;


architecture SCHEMATIC of dcount16 is

	constant VCC : STD_LOGIC := '1';
   signal      N_1 : STD_LOGIC;
   signal      N_2 : STD_LOGIC;
   signal      N_3 : STD_LOGIC;
   signal Q_DUMMY : STD_LOGIC_VECTOR  (15 downto 0);

   component DCNTX4B
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (3 downto 0);
                 ENG : In    STD_LOGIC;
                 ENP : In    STD_LOGIC;
                 ENT : In    STD_LOGIC;
                LOAD : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0);
                 RCO : Out   STD_LOGIC );
   end component;

   component DCNTX4C
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (3 downto 0);
                 ENG : In    STD_LOGIC;
                 ENP : In    STD_LOGIC;
                 ENT : In    STD_LOGIC;
                LOAD : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

begin


   Q(15 downto 0) <= Q_DUMMY(15 downto 0);
   I1 : DCNTX4B
      Port Map ( CLK=>CLK, CLR=>CLR, D(3 downto 0)=>D(11 downto 8),
                 ENG=>EN, ENP=>N_2, ENT=>N_2, LOAD=>LOAD,
                 Q(3 downto 0)=>Q_DUMMY(11 downto 8), RCO=>N_1 );
   I2 : DCNTX4B
      Port Map ( CLK=>CLK, CLR=>CLR, D(3 downto 0)=>D(7 downto 4),
                 ENG=>EN, ENP=>N_3, ENT=>N_3, LOAD=>LOAD,
                 Q(3 downto 0)=>Q_DUMMY(7 downto 4), RCO=>N_2 );
   I3 : DCNTX4B
      Port Map ( CLK=>CLK, CLR=>CLR, D(3 downto 0)=>D(3 downto 0),
                 ENG=>EN, ENP=>VCC, ENT=>VCC, LOAD=>LOAD,
                 Q(3 downto 0)=>Q_DUMMY(3 downto 0), RCO=>N_3 );
   I4 : DCNTX4C
      Port Map ( CLK=>CLK, CLR=>CLR, D(3 downto 0)=>D(15 downto 12),
                 ENG=>EN, ENP=>N_1, ENT=>N_1, LOAD=>LOAD,
                 Q(3 downto 0)=>Q_DUMMY(15 downto 12) );

end SCHEMATIC;