lcnt64.vhd

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· VHDL 代码 · 共 47 行

-------------------------------------------------------------------------
-- File : lcnt64.vhd
-- Design Date: Sep 14, 1998
-- Creation Date: Thu Jan 25 18:43:16 2001
-- Created By SpDE Version: SpDE 8.2 
-- Author: Randy Oyadomari, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description: This is the counter for generating the read
-- and write addresses in the FIFOs.
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

-- inputs: clk,rst,up,dn
-- outputs: =q[7:1]=

entity lcnt64 is
  port (clk,rst,up,dn : in std_logic;
        q : out std_logic_vector(7 downto 1)
       );
end lcnt64;

architecture lcnt64_1 of lcnt64 is
  signal q_int : std_logic_vector(7 downto 1);
  signal updn : std_logic_vector(1 downto 0);
begin

  q <= q_int;
  updn <= up&dn;

  process (clk,rst) begin
    if (rst = '1') then
      q_int <= "1101010" after 1 ns;  --6A hex
    elsif (clk'event and clk='1') then
      case updn is
		  when "00" => q_int <= q_int after 1 ns;
		  when "01" => q_int <= q_int(6 downto 1) & (q_int(7) xor q_int(6)) after 1 ns;
		  when "10" => q_int <= (q_int(1) xor q_int(7)) & q_int(7 downto 2) after 1 ns;
		  when "11" => q_int <= q_int after 1 ns;
              when others => q_int <= q_int after 1 ns;
      end case;
    end if;
  end process;

end lcnt64_1;