pci_access.tb

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TB 代码 · 共 336 行

--------------------------------------------------------------------------------
--
-- File : pci_access.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	Procedure that sets up and executes a PCI transaction via the
--	PCI master model (pci_mast).
--
-- Hierarchy:
--	This file provides a package to be used in pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pci_pack.all;



package pci_access_package is

procedure pci_access( --inputs to the procedure
                      address : in std_logic_vector(63 downto 0);
                      data : in std_logic_vector(63 downto 0);
					  pci_command : in std_logic_vector(3 downto 0);
					  byte_enable : in std_logic_vector(7 downto 0);
					  --addr_parity : in std_logic;
					  --data_parity : in std_logic;
					  dword_count : in integer;
					  initial_waitstates : in integer;
					  subsequent_waitstates : in integer;
					  bad_par_phase : in integer;
					  m64bit : in std_logic;
					  --pass_fail : inout std_logic;
					  quiet : in std_logic;

                      --outputs from the procedure
                      SIGNAL master1_start_bit : OUT std_logic;
                      SIGNAL master1_done_bit : IN std_logic;
                      SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
                      SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
                      SIGNAL master1_dword_count : OUT integer;
					  SIGNAL master1_initial_data_delay : OUT integer;
                      SIGNAL master1_next_data_delay : OUT integer;
					  signal master1_bad_parity_phase : out integer;
                      SIGNAL master1_m64bit : OUT std_logic;
                      SIGNAL master1_quiet : OUT std_logic;
                      SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
                      SIGNAL data_array : OUT DATA_ARRAY_TYPE;
					  SIGNAL CLK : IN std_logic
					);

procedure wait_for_clocks ( signal CLK : in std_logic;
                              num_clks : in integer
                            );	
							
procedure cfg_read(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in  std_logic_vector(31 downto 0);
	  expected_data: in  std_logic_vector(31 downto 0);
      data         : out std_logic_vector(31 downto 0)
);
procedure cfg_write(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in std_logic_vector(31 downto 0);
      byte_enable  : in std_logic_vector(3 downto 0);
      data         : in std_logic_vector(31 downto 0)
);
procedure mem32_single_read(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in  std_logic_vector(31 downto 0);
	  expected_data: in std_logic_vector(31 downto 0);
      data         : out std_logic_vector(31 downto 0)
);
procedure mem32_single_write(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in std_logic_vector(31 downto 0);
      byte_enable  : in std_logic_vector(3 downto 0);
      data         : in std_logic_vector(31 downto 0)
);
procedure mem32_burst_read(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in  std_logic_vector(31 downto 0);	
	  dword_count  : in  integer;
      data_check   : in  DATA_ARRAY_TYPE;
	  ok           : out boolean
);
procedure mem32_burst_write(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in std_logic_vector(31 downto 0);
	  dword_count  : in  integer;
      be_array     : in BYTE_ARRAY_TYPE;
      data_array   : in DATA_ARRAY_TYPE
);


end pci_access_package;



package body pci_access_package is

procedure pci_access( --inputs to the procedure
                      address : in std_logic_vector(63 downto 0);
                      data : in std_logic_vector(63 downto 0);
					  pci_command : in std_logic_vector(3 downto 0);
					  byte_enable : in std_logic_vector(7 downto 0);
					  --addr_parity : in std_logic;
					  --data_parity : in std_logic;
					  dword_count : in integer;
					  initial_waitstates : in integer;
					  subsequent_waitstates : in integer;
					  bad_par_phase : in integer;
					  m64bit : in std_logic;
					  --pass_fail : inout std_logic;
					  quiet : in std_logic;

                      --outputs from the procedure
                      SIGNAL master1_start_bit : OUT std_logic;
                      SIGNAL master1_done_bit : IN std_logic;
                      SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
                      SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
                      SIGNAL master1_dword_count : OUT integer;
					  SIGNAL master1_initial_data_delay : OUT integer;
                      SIGNAL master1_next_data_delay : OUT integer;
					  signal master1_bad_parity_phase : out integer;
                      SIGNAL master1_m64bit : OUT std_logic;
                      SIGNAL master1_quiet : OUT std_logic;
                      SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
                      SIGNAL data_array : OUT DATA_ARRAY_TYPE;
					  SIGNAL CLK : IN std_logic
					) is
begin

  wait until rising_edge(CLK);
  master1_addr <= address(63 downto 0);
  master1_command <= pci_command(3 downto 0);
  master1_dword_count <= dword_count;
  master1_initial_data_delay <= initial_waitstates;
  master1_next_data_delay <= subsequent_waitstates;
  master1_bad_parity_phase <= bad_par_phase;
  master1_m64bit <= m64bit;
  master1_quiet <= quiet;
  if (dword_count < 3) then
    data_array(0) <= data(31 downto 0);
    data_array(1) <= data(63 downto 32);
    be_array(0) <= byte_enable(3 downto 0);
    be_array(1) <= byte_enable(7 downto 4);
  end if;
    master1_start_bit <= '1';
  wait until rising_edge(CLK);
    master1_start_bit <= '0';
  wait until master1_done_bit = '1';
end pci_access;

procedure wait_for_clocks ( signal CLK : in std_logic;
                              num_clks : in integer
                            ) is
    variable i : integer;
  begin
    for i in 1 to num_clks loop
      wait until rising_edge(CLK);
    end loop;
end wait_for_clocks;

procedure cfg_read(	   
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in  std_logic_vector(31 downto 0);
      expected_data: in  std_logic_vector(31 downto 0);
      data         : out std_logic_vector(31 downto 0)
) is
begin
  wait until rising_edge(mst_resp.CLK);
  mst_req.addr <= X"0000_0000" & addr(31 downto 2) & "00";
  mst_req.command <= CONFIG_READ;
  mst_req.dword_count <= 1;
  mst_req.m64bit <= '0';
--  mst_req.data_array(0) <= (others => '0');
--  mst_req.data_array(0) <= data;
  mst_req.data_array(0) <= expected_data;
  mst_req.be_array(0) <= (others => '1');
  mst_req.start <= '1';
  wait until rising_edge(mst_resp.CLK);
    mst_req.start <= '0';
  wait until mst_resp.done = '1';	 
  if addr(2) = '0' then
     data := mst_resp.last_data(31 downto 0);
  else
     data := mst_resp.last_data(63 downto 32);
  end if;
end cfg_read;

procedure cfg_write(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in std_logic_vector(31 downto 0);
      byte_enable  : in std_logic_vector(3 downto 0);
      data         : in std_logic_vector(31 downto 0)
) is
begin
  wait until rising_edge(mst_resp.CLK);
  mst_req.addr <= X"0000_0000" & addr(31 downto 2) & "00";
  mst_req.command <= CONFIG_WRITE;
  mst_req.dword_count <= 1;
  mst_req.m64bit <= '0';
  mst_req.data_array(0) <= data;
  mst_req.be_array(0) <= byte_enable;
  mst_req.start <= '1';
  wait until rising_edge(mst_resp.CLK);
    mst_req.start <= '0';
  wait until mst_resp.done = '1';
end cfg_write;

procedure mem32_single_read(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in  std_logic_vector(31 downto 0);
	  expected_data: in std_logic_vector(31 downto 0);
      data         : out std_logic_vector(31 downto 0)
) is
begin
  wait until rising_edge(mst_resp.CLK);
  mst_req.addr <= X"0000_0000" & addr(31 downto 2) & "00";
  mst_req.command <= MEM_READ;
  mst_req.dword_count <= 1;
  mst_req.m64bit <= '0';
--  mst_req.data_array(0) <= (others => '0'); 
  mst_req.data_array(0) <= expected_data;
  mst_req.be_array(0) <= (others => '1');
  mst_req.start <= '1';
  wait until rising_edge(mst_resp.CLK);
    mst_req.start <= '0';
  wait until mst_resp.done = '1';
  if addr(2) = '0' then
     data := mst_resp.last_data(31 downto 0);
  else
     data := mst_resp.last_data(63 downto 32);
  end if;
end mem32_single_read;

procedure mem32_single_write(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in std_logic_vector(31 downto 0);
      byte_enable  : in std_logic_vector(3 downto 0);
      data         : in std_logic_vector(31 downto 0)
) is
begin
  wait until rising_edge(mst_resp.CLK);
  mst_req.addr <= X"0000_0000" & addr(31 downto 2) & "00";
  mst_req.command <= MEM_WRITE;
  mst_req.dword_count <= 1;
  mst_req.m64bit <= '0';
  mst_req.data_array(0) <= data;
  mst_req.be_array(0) <= byte_enable;
  mst_req.start <= '1';
  wait until rising_edge(mst_resp.CLK);
    mst_req.start <= '0';
  wait until mst_resp.done = '1';
end mem32_single_write;

procedure mem32_burst_read(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in  std_logic_vector(31 downto 0);	
	  dword_count  : in  integer;
      data_check   : in  DATA_ARRAY_TYPE;
	  ok           : out boolean
) is
begin
  wait until rising_edge(mst_resp.CLK);
  mst_req.addr <= X"0000_0000" & addr(31 downto 2) & "00";
  mst_req.command <= MEM_READ;
  mst_req.dword_count <= dword_count;
  mst_req.m64bit <= '0';
  mst_req.data_array <= data_check;
  mst_req.be_array <= (others => (others => '1'));
  mst_req.start <= '1';
  wait until rising_edge(mst_resp.CLK);
    mst_req.start <= '0';
  wait until mst_resp.done = '1';
  if mst_resp.pass = '1' then
	  ok := true;
  else
	  ok := false;
  end if;
end mem32_burst_read;

procedure mem32_burst_write(
signal  mst_req   : out MASTER_REQ_TYPE;
signal  mst_resp   : in MASTER_RESP_TYPE;
      addr         : in std_logic_vector(31 downto 0);
	  dword_count  : in  integer;
      be_array     : in BYTE_ARRAY_TYPE;
      data_array   : in DATA_ARRAY_TYPE
) is
begin
  wait until rising_edge(mst_resp.CLK);
  mst_req.addr <= X"0000_0000" & addr(31 downto 2) & "00";
  mst_req.command <= MEM_WRITE;
  mst_req.dword_count <= dword_count;
  mst_req.m64bit <= '0';
  mst_req.data_array <= data_array;
  mst_req.be_array <= be_array;
  mst_req.start <= '1';
  wait until rising_edge(mst_resp.CLK);
    mst_req.start <= '0';
  wait until mst_resp.done = '1';
end mem32_burst_write;




end package body pci_access_package;