cardbus_5632.rpt

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· RPT 代码 · 共 149 行

++++++++++++++++++++++
| Design Information |
++++++++++++++++++++++
Design:            CARDBUS_5632
SpDE Version:      SpDE 9.5.4 Internal Build1
Report Generated:  Thu Apr 08 11:18:23 2004
CHIP Last Updated: Wed Apr 07 18:52:17 2004
Part Type:         ql5632-33
Speed Grade:       B
Operating Range:   Commercial
Package Type:      280 PIN PBGA
ESP Version :      pci32_25um v1_2
Link Check Sum: Undetermined: sequencer has not yet been run

+++++++++++++++++++++++++++
| Utilization Information |
+++++++++++++++++++++++++++
Utilized cells (preplacement):                 545 of     772  (70.6%)
Utilized cells (postplacement):                674 of     772  (87.3%)
Utilized Logic cell Frags (preplacement):     2463 of    4632  (53.2%)
Utilized Logic cell Frags (postplacement):    2696 of    4632  (58.2%)
Utilized Fragment A :                          542
Utilized Fragment F :                          516
Utilized Fragment O :                          565
Utilized Fragment N :                          599
IO control cells:                                0 of      16  (0.0%)
Clock only cells:                                1 of       8  (12.5%)
Bi directional cells:                          106 of     115  (92.2%)
RAM cells:                                       9 of      18  (50.0%)
ECU cells:                                       0 of      10  (0.0%)
PLL cells:                                       0 of       4  (0.0%)
Flip-Flop of IO cells:                          36 of     115  (31.3%)
1st Flip-Flop of Logic cells:                  203 of     772  (26.3%)
2nd Flip-Flop of Logic cells:                  271 of     772  (35.1%)
Routing resources:                           25923 of   78139  (33.2%)
ViaLink resources:                           22888 of 2096022  (1.1%)



+++++++++++++++++++++++++++++++++++++++++++
| Clock Network Utilization by clock pads |
+++++++++++++++++++++++++++++++++++++++++++
	Clock Network                  Net                                  Pin      Quad                  Load    
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	PLLMUX_BR2                     local_clock                          V11      Bottom Right           76      
	PLLMUX_TR2                     local_clock                          V11      Top Right              5       


+++++++++++++++++++++++++++++++++++++++++++++++
| Clock Network Utilization by Internal Logic |
+++++++++++++++++++++++++++++++++++++++++++++++
	Clock Network                  Net                                  Driver   Quad                  Load    
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	HSCKMUX_TR7                    n_20                                 V4       Top Right              3       
	HSCKMUX_BL7                    pci_reset                            N5       Bottom Left            110     
	HSCKMUX_BR7                    n_20                                 V4       Bottom Right           64      
	HSCKMUX_TL6                    pci_reset                            N5       Top Left               48      
	HSCKMUX_TR6                    pci_reset                            N5       Top Right              109     
	HSCKMUX_BR6                    n_19                                 V4       Bottom Right           33      
	HSCKMUX_BR0                    fpga_oe_i_i_LRBUF914Bottom Right     AI13     Bottom Right           32      
	HSCKMUX_BR1                    pci_reset                            N5       Bottom Right           67      


++++++++++++++++++++++++++++++++++++
| Clock Network Utilization by PLL |
++++++++++++++++++++++++++++++++++++

|Available HSCK Clock Networks|
	Quad TOP LEFT     : 	3 of 4 QuadNets available	(75.0%)
	Quad TOP RIGHT    : 	3 of 5 QuadNets available	(60.0%)
	Quad BOTTOM LEFT  : 	4 of 5 QuadNets available	(80.0%)
	Quad BOTTOM RIGHT : 	1 of 5 QuadNets available	(20.0%)




++++++++++++++++++
| Timing Results |
++++++++++++++++++

Summary:

Longest Pad to Pad: 6.5 ns (pad_intr -- pad_CINT_n)

Clock                               Frequency       Setup Time      Clock to Out   
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
CLK (ESP: PCI_clock)             43 MHz / 23.1 ns      7.1 ns         19.2 ns
lclk                            102 MHz /  9.8 ns      2.9 ns         10.7 ns


Inter Clock Domain Delay Matrix
+++++++++++++++++++++++++++++++

Clock0 = CLK 
Clock1 = lclk 

 
          Clock0    Clock1  
Clock0   23.1 ns   18.4 ns
Clock1    8.1 ns    9.8 ns

++++++++++++++++++++++++++++++++++++
| Tools run on design CARDBUS_5632 |
++++++++++++++++++++++++++++++++++++
partdef         6.0    
design          3.0    
logic optimizer 9.54    Mode = Quality Goal = Speed IgnorePack = FALSE UseNonBondedPads = TRUE Run Time 0:00:27
placer          9.54    Seed = 42 Mode = Quality Run Time 0:27:24
router          9.54    Seed = 42 Run Time 0:01:42
delay modeler   9.54    Mode = Commercial Corner = Worst SpeedGrade = B LowPower = FALSE Run Time 0:00:25
back annotation 9.54    Run Time 0:07:30
verifier        9.54    Strip = TRUE RemoveBuffersOnLoad = TRUE
auto buffer     9.54   


+++++++++++++
| Pin Table |
+++++++++++++
Display Pin Info option is FALSE.
Pin information will not be displayed.

++++++++++++++++++++
| Fixed Flip Flops |
++++++++++++++++++++
None


+++++++++++++++++++
| Fixed RAM cells |
+++++++++++++++++++
None


+++++++++++++++++++
| Fixed ECU cells |
+++++++++++++++++++
None


+++++++++++++++++++++++++++++++++++++
| Nets Removed by Technology Mapper |
+++++++++++++++++++++++++++++++++++++
Removed Nets option is FALSE.
Removed Nets information will not be displayed.



++++++++++  The end of report file  ++++++++++