cfgtaddr_cardbus.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

    begin
        if PCI_reset = '1' then
            ParErrorDetected     <= '0';
            SignaledSystemError  <= '0';
            ReceivedMasterAbort  <= '0';
            ReceivedTargetAbort  <= '0';
			-- uncomment the following block for designs that are capable of generating target aborts
			-- SignaledTargetAbort <= '0';
            DataParErrorDetected <= '0';
        elsif PCI_clock'event and PCI_clock = '1' then
            if (WrData(31) and StatusRegWE) = '1' then ParErrorDetected   <= '0';
            elsif PERR_Det = '1' and (WrData(31) and StatusRegWE) = '0' then
                ParErrorDetected    <= '1';
            end if;

            if (WrData(30) and StatusRegWE) = '1' then SignaledSystemError <= '0';
            elsif SERR_Sig = '1' and (WrData(30) and StatusRegWE) = '0' then
                SignaledSystemError <= '1';
            end if;
        
            if (WrData(29) and StatusRegWE) = '1' then ReceivedMasterAbort <= '0';
            elsif TTO_Det = '1' and (WrData(29) and StatusRegWE) = '0' then
				if MstSC = '0' then
	                ReceivedMasterAbort <= '1';
				end if;
            end if;

            if (WrData(28) and StatusRegWE) = '1' then ReceivedTargetAbort <= '0';
            elsif Tabort_Det = '1' and (WrData(28) and StatusRegWE) = '0' then
                ReceivedTargetAbort <= '1';
            end if;

			-- uncomment the following block for designs that are capable of generating target aborts
			-- Usr_Abort is the signal connected to the Usr_Abort port of the PCI core
            -- if (WrData(27) and StatusRegWE) = '1' then SignaledTargetAbort <= '0';
            -- elsif Usr_Abort = '1' and (WrData(27) and StatusRegWE) = '0' then
            --     SignaledTargetAbort <= '1';
            -- end if;

            if (WrData(24) and StatusRegWE) = '1' then DataParErrorDetected <= '0';
            elsif MstPERR_Det = '1' and (WrData(24) and StatusRegWE) = '0' then
                DataParErrorDetected <= '1';
            end if;
        
        end if;
    end process;


    -- Command register, offset 04h

    CommandLoWE <= IncrAddr and Cfg_Write and not CBE(0) when cfgadr = "0001" else '0'; 
    CommandHiWE <= IncrAddr and Cfg_Write and not CBE(1) when cfgadr = "0001" else '0'; 
 
    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then
            MemEnable <= '0';
            BusMasterEnable <= '0';
			SpecialCycleEnable <= '0';
			MemWrAndInvalidateEnable <= '0';
            ParityErrorEnable <= '0';
        elsif PCI_clock'event and PCI_clock = '1' then
            if CommandLoWE = '1' then
                MemEnable <= WrData(1);
                BusMasterEnable <= WrData(2);
				SpecialCycleEnable <= WrData(3);
				MemWrAndInvalidateEnable <= WrData(4);
                ParityErrorEnable <= WrData(6);
            end if;
        end if;
    end process;

    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then SERREnable <= '0';
        elsif PCI_clock'event and PCI_clock = '1' then
            if CommandHiWE = '1' then SERREnable <= WrData(8); end if;
        end if;
    end process;


    -- Latency Timer, offset 0Ch
    LatTimerWE <= IncrAddr and Cfg_Write and not CBE(1) when cfgadr = "0011" else '0';

    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then LatTimer(7 downto 0) <= "00000000";
        elsif PCI_clock'event and PCI_clock = '1' then
            if LatTimerWE = '1' then LatTimer(7 downto 0) <= WrData(15 downto 8); end if;
        end if;
    end process;
        

    -- Cache Line Size Register, offset 0Ch
    CacheLineSizeWE <= IncrAddr and Cfg_Write and not CBE(0) when cfgadr = "0011" else '0';

    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then CacheLineSize(7 downto 2) <= "000000";
        elsif PCI_clock'event and PCI_clock = '1' then
            if CacheLineSizeWE = '1' then CacheLineSize(7 downto 2) <= WrData(7 downto 2); end if;
        end if;
    end process;
        

    -- Base Address Register 0, offset 10h

    BAR0WE <= IncrAddr and Cfg_Write when cfgadr = "0100" else '0';

    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then BAR0_reg <= (others => '0');
        elsif PCI_clock'event and PCI_clock = '1' then 
            if BAR0WE = '1' and not CBE(3) = '1' then
                BAR0_reg(31 downto 24) <= WrData(31 downto 24);
            end if;

            if BAR0WE = '1' and not CBE(2) = '1' then
                BAR0_reg(23 downto 16) <= WrData(23 downto 16);
            end if;

            if BAR0WE = '1' and not CBE(1) = '1' then
                BAR0_reg(15 downto 10) <= WrData(15 downto 10);
            end if;
        end if;
    end process;

    -- CT for CIS BAR5, offset 24h

    BAR5WE <= IncrAddr and Cfg_Write when cfgadr = "1001" else '0';

    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then BAR5_reg <= (others => '0');
        elsif PCI_clock'event and PCI_clock = '1' then 
            if BAR5WE = '1' and not CBE(3) = '1' then
                BAR5_reg(31 downto 24) <= WrData(31 downto 24);
            end if;

            if BAR5WE = '1' and not CBE(2) = '1' then
                BAR5_reg(23 downto 16) <= WrData(23 downto 16);
            end if;

            if BAR5WE = '1' and not CBE(1) = '1' then
                BAR5_reg(15 downto 10) <= WrData(15 downto 10);
            end if;
        end if;
    end process;

    -- Interrupt Line, offset 3Ch
    -- Remove the following Comments for Interrupt Support

    -- IntLineWE <= IncrAddr and Cfg_Write and not CBE(0) when cfgadr = "1111" else '0';
    
    -- process (PCI_clock, PCI_reset)
    -- begin
    --     if PCI_reset = '1' then IntLine <= X"00";
    --     elsif PCI_clock'event and PCI_clock = '1' then
    --         if IntLineWE = '1' then IntLine <= WrData(7 downto 0);
    --     end if;
    -- end process;

    -- Configuration Space Output Mux
    process (UsrAddr_local(8 downto 2))
    begin
        if UsrAddr_local(8 downto 6) = "000" then
            cfgadr <= UsrAddr_local(5 downto 2);
        else
            cfgadr <= "1110";  -- Assign to a reserved address (38h)if not in a legal address range
                               -- This saves logic and assures that the read results in zeros
        end if;
    end  process;

	process (cfgadr, Dev_Vend, Stat_Cmd, Class_RevID, BIST_Hdr_Lat_Cache, BAR0,
			 SubsysID_SubsysVendID, Lat_Gnt_IntPin_IntLine, BAR5)
    begin
        case cfgadr is
            when "0000" => CfgData <= Dev_Vend;
            when "0001" => CfgData <= Stat_Cmd;
            when "0010" => CfgData <= Class_RevID;
            when "0011" => CfgData <= BIST_Hdr_Lat_Cache;
            when "0100" => CfgData <= BAR0;
            when "1001" => CfgData <= BAR5;
            when "1010" => CfgData <= Cardbus_CIS;
            when "1011" => CfgData <= SubsysID_SubsysVendID;
            when "1100" => CfgData <= Expansion_ROM;
            when "1111" => CfgData <= Lat_Gnt_IntPin_IntLine;
            when others => CfgData <= (others => '0');
        end case;
    end process;


    -- *** assignments to output ports
    CmdReg <= Stat_Cmd(15 downto 0);
    LatTimerReg <= LatTimer;
	CacheLineSizeReg <= CacheLineSize;


    -- *****************************************
    -- ***  target address register/counter  ***
    -- *****************************************
    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then UsrAddr_local(BAR0_size-1 downto 0) <= (others => '0') after 1 ns;
        elsif PCI_clock'event and PCI_clock = '1' then
            if LoadAddr = '1' then 
                UsrAddr_local(BAR0_size-1 downto 0) <= WrData(BAR0_size-1 downto 0) after 1 ns;
            elsif IncrAddr = '1' then
                UsrAddr_local(BAR0_size-1 downto 2) <=
                std_logic_vector(unsigned(UsrAddr_local(BAR0_size-1 downto 2)) + 1) after 1 ns;
            end if;
        end if;
    end process;

    Addr_Hit <= BAR0_Hit_int or BAR5_Hit_int;
	BAR0_Hit_int <= MemEnable when WrData(31 downto BAR0_size) = BAR0_reg else '0';
	BAR5_Hit_int <=	MemEnable when WrData(31 downto BAR5_size) = BAR5_reg else '0';
	BAR0_Hit <= BAR0_Hit_int;
	BAR5_Hit <= BAR5_Hit_int;
--	CIS_Hit <= CIS_Hit_int;

    process (PCI_clock, PCI_reset)
    begin
        if PCI_reset = '1' then Usr_Stop <= '0';
        elsif PCI_clock'event and PCI_clock = '1' then
            if IncrAddr = '1' and (not (UsrAddr_local(1 downto 0) = "00") or 
                            UsrAddr_local(BAR0_size-1 downto 2) = ALL_ONES) then
                Usr_Stop <= '1';
            else Usr_Stop <= '0';
            end if;
        end if;
    end process;

    -- ************************
    -- ***  command decode  ***
    -- ************************

    -- map usr_read to mem read (0110), mem read mult (1100), or mem read line (1110)
    Usr_RdCmd <= '1' 
        when CBE(2 downto 0) = "110" or CBE(3 downto 2) & CBE(0) = "110"
        else '0';

    -- map usr_write to mem write (0111) and mem write and invalidate (1111)
    Usr_WrCmd <= '1' when CBE(2 downto 0) = "111" else '0';


end behavioral;