cfgtaddr_5632_280_pkg.vhd

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· VHDL 代码 · 共 26 行

library IEEE;
use IEEE.std_logic_1164.all;

package cfgtaddr_5632_280_pkg is

constant DeviceID : std_logic_vector (15 downto 0) := x"001E";
constant VendorID : std_logic_vector (15 downto 0) := x"11E3";
constant ClassCode : std_logic_vector (23 downto 0):= x"FF0000";
constant RevisionID : std_logic_vector (7 downto 0):= x"00";
constant BIST : std_logic_vector (7 downto 0)      := x"00";
constant HeaderType : std_logic_vector (7 downto 0):= x"00";
constant LatTimer : std_logic_vector (7 downto 0) := x"00";
constant CacheLineSize : std_logic_vector (7 downto 0) := x"00";
constant BAR0 : integer := 10; --Corresponds to 1KB memory
constant BAR5 : integer := 10; --Corresponds to 1KB memory
constant CardBus_CIS : std_logic_vector (31 downto 0) := x"00000000";
constant SubsysID : std_logic_vector (15 downto 0) := x"0002";
constant SubsysVendID : std_logic_vector (15 downto 0):= x"11E3";
constant Expansion_ROM : std_logic_vector (31 downto 0):= x"00000000";
constant MaxLat : std_logic_vector (7 downto 0) := x"10";
constant MinGnt : std_logic_vector (7 downto 0) := x"08";
constant IntPin : std_logic_vector (7 downto 0) := x"00";
constant IntLine : std_logic_vector (7 downto 0) := x"00";

end cfgtaddr_5632_280_pkg;