📄 pci5632_280.vhd
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FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(22),
FFQ=>WrBuff_in(22), Q=>WrD(22) );
ladpadsQ21Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(21), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(21),
FFQ=>WrBuff_in(21), Q=>WrD(21) );
ladpadsQ20Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(20), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(20),
FFQ=>WrBuff_in(20), Q=>WrD(20) );
ladpadsQ19Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(19), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(19),
FFQ=>WrBuff_in(19), Q=>WrD(19) );
ladpadsQ18Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(18), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(18),
FFQ=>WrBuff_in(18), Q=>WrD(18) );
ladpadsQ17Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(17), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(17),
FFQ=>WrBuff_in(17), Q=>WrD(17) );
ladpadsQ16Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(16), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(16),
FFQ=>WrBuff_in(16), Q=>WrD(16) );
ladpadsQ15Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(15), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(15),
FFQ=>WrBuff_in(15), Q=>WrD(15) );
ladpadsQ14Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(14), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(14),
FFQ=>WrBuff_in(14), Q=>WrD(14) );
ladpadsQ13Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(13), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(13),
FFQ=>WrBuff_in(13), Q=>WrD(13) );
ladpadsQ12Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(12), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(12),
FFQ=>WrBuff_in(12), Q=>WrD(12) );
ladpadsQ11Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(11), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(11),
FFQ=>WrBuff_in(11), Q=>WrD(11) );
ladpadsQ10Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(10), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(10),
FFQ=>WrBuff_in(10), Q=>WrD(10) );
ladpadsQ9Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(9), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(9),
FFQ=>WrBuff_in(9), Q=>WrD(9) );
ladpadsQ8Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(8), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(8),
FFQ=>WrBuff_in(8), Q=>WrD(8) );
ladpadsQ7Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(7), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(7),
FFQ=>WrBuff_in(7), Q=>WrD(7) );
ladpadsQ6Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(6), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(6),
FFQ=>WrBuff_in(6), Q=>WrD(6) );
ladpadsQ5Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(5), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(5),
FFQ=>WrBuff_in(5), Q=>WrD(5) );
ladpadsQ4Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(4), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(4),
FFQ=>WrBuff_in(4), Q=>WrD(4) );
ladpadsQ3Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(3), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(3),
FFQ=>WrBuff_in(3), Q=>WrD(3) );
ladpadsQ2Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(2), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(2),
FFQ=>WrBuff_in(2), Q=>WrD(2) );
ladpadsQ1Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(1), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(1),
FFQ=>WrBuff_in(1), Q=>WrD(1) );
ladpadsQ0Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(0), EN=>N_10, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(0),
FFQ=>WrBuff_in(0), Q=>WrD(0) );
I189 : CKPAD_25UM
Port Map ( P=>lclk, Q=>local_clock );
I218 : OUTPAD_25UM
Port Map ( A=>N_19, P=>mrs_DUMMY );
ledpadsQ7Q : OUTPAD_25UM
Port Map ( A=>mxledoi(7), P=>led_DUMMY(7) );
ledpadsQ6Q : OUTPAD_25UM
Port Map ( A=>mxledoi(6), P=>led_DUMMY(6) );
ledpadsQ5Q : OUTPAD_25UM
Port Map ( A=>mxledoi(5), P=>led_DUMMY(5) );
ledpadsQ4Q : OUTPAD_25UM
Port Map ( A=>mxledoi(4), P=>led_DUMMY(4) );
ledpadsQ3Q : OUTPAD_25UM
Port Map ( A=>mxledoi(3), P=>led_DUMMY(3) );
ledpadsQ2Q : OUTPAD_25UM
Port Map ( A=>mxledoi(2), P=>led_DUMMY(2) );
ledpadsQ1Q : OUTPAD_25UM
Port Map ( A=>mxledoi(1), P=>led_DUMMY(1) );
ledpadsQ0Q : OUTPAD_25UM
Port Map ( A=>mxledoi(0), P=>led_DUMMY(0) );
I201 : OUTPAD_25UM
Port Map ( A=>N_18, P=>wen_DUMMY );
I202 : OUTPAD_25UM
Port Map ( A=>N_17, P=>ren_DUMMY );
I203 : OUTPAD_25UM
Port Map ( A=>fifo_oe_n, P=>oe_DUMMY );
I204 : OUTPAD_25UM
Port Map ( A=>ldn, P=>ld_DUMMY );
I205 : INPADFF_25UM
Port Map ( FFCLK=>local_clock, FFCLR=>GND, FFEN=>VCC, P=>ir_n,
FFQ=>irn_in, Q=>open );
I207 : INPADFF_25UM
Port Map ( FFCLK=>local_clock, FFCLR=>GND, FFEN=>VCC, P=>or_n,
FFQ=>orn_in, Q=>open );
I208 : INPADFF_25UM
Port Map ( FFCLK=>local_clock, FFCLR=>GND, FFEN=>VCC, P=>pae_n,
FFQ=>paen_in, Q=>open );
I209 : INPADFF_25UM
Port Map ( FFCLK=>local_clock, FFCLR=>GND, FFEN=>VCC, P=>paf_n,
FFQ=>pafn_in, Q=>open );
I165 : AND3I2
Port Map ( A=>WrBuff_fullN, B=>fpga_oe, C=>N_11, Q=>N_12 );
I166 : DFF
Port Map ( CLK=>local_clock, D=>fpga_oe, Q=>N_11 );
I159 : AND4I3
Port Map ( A=>PCI_Cmd(0), B=>PCI_Cmd(1), C=>PCI_Cmd(2),
D=>PCI_Cmd(3), Q=>N_8 );
I160 : DFFE
Port Map ( CLK=>PCI_clock, D=>N_8, EN=>Mst_Burst_Req, Q=>MstSC );
I157 : AND3I1
Port Map ( A=>PCI_Cmd(0), B=>Mst_WrData_Rdy, C=>Mst_Data_Sel,
Q=>N_6 );
I153 : OR3I0
Port Map ( A=>N_4, B=>Mst_TTO_Det, C=>N_5, Q=>DMA_Error );
I158 : AND2I1
Port Map ( A=>Mst_RdData_Valid, B=>Mst_Data_Sel, Q=>N_7 );
I154 : AND2I1
Port Map ( A=>BEFIFO_pop, B=>BEFIFO_emptyn, Q=>N_5 );
I163 : AND2I0
Port Map ( A=>Mst_WrData_Rdy, B=>Mst_BE_Sel, Q=>BEFIFO_pop );
I147 : AND2I0
Port Map ( A=>N_1, B=>RdBuff_full, Q=>N_4 );
I145 : OR2I0
Port Map ( A=>Cfg_Stop, B=>Prog_Stop, Q=>Usr_Stop );
I161 : OR2I0
Port Map ( A=>Usr_Write, B=>Cfg_Write, Q=>N_9 );
Mst_WrData_MuxQ31Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(31), B=>Mst_WrData_Reg(31),
S=>Mst_Data_Sel, Q=>Mst_WrData(31) );
Mst_WrData_MuxQ30Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(30), B=>Mst_WrData_Reg(30),
S=>Mst_Data_Sel, Q=>Mst_WrData(30) );
Mst_WrData_MuxQ29Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(29), B=>Mst_WrData_Reg(29),
S=>Mst_Data_Sel, Q=>Mst_WrData(29) );
Mst_WrData_MuxQ28Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(28), B=>Mst_WrData_Reg(28),
S=>Mst_Data_Sel, Q=>Mst_WrData(28) );
Mst_WrData_MuxQ27Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(27), B=>Mst_WrData_Reg(27),
S=>Mst_Data_Sel, Q=>Mst_WrData(27) );
Mst_WrData_MuxQ26Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(26), B=>Mst_WrData_Reg(26),
S=>Mst_Data_Sel, Q=>Mst_WrData(26) );
Mst_WrData_MuxQ25Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(25), B=>Mst_WrData_Reg(25),
S=>Mst_Data_Sel, Q=>Mst_WrData(25) );
Mst_WrData_MuxQ24Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(24), B=>Mst_WrData_Reg(24),
S=>Mst_Data_Sel, Q=>Mst_WrData(24) );
Mst_WrData_MuxQ23Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(23), B=>Mst_WrData_Reg(23),
S=>Mst_Data_Sel, Q=>Mst_WrData(23) );
Mst_WrData_MuxQ22Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(22), B=>Mst_WrData_Reg(22),
S=>Mst_Data_Sel, Q=>Mst_WrData(22) );
Mst_WrData_MuxQ21Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(21), B=>Mst_WrData_Reg(21),
S=>Mst_Data_Sel, Q=>Mst_WrData(21) );
Mst_WrData_MuxQ20Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(20), B=>Mst_WrData_Reg(20),
S=>Mst_Data_Sel, Q=>Mst_WrData(20) );
Mst_WrData_MuxQ19Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(19), B=>Mst_WrData_Reg(19),
S=>Mst_Data_Sel, Q=>Mst_WrData(19) );
Mst_WrData_MuxQ18Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(18), B=>Mst_WrData_Reg(18),
S=>Mst_Data_Sel, Q=>Mst_WrData(18) );
Mst_WrData_MuxQ17Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(17), B=>Mst_WrData_Reg(17),
S=>Mst_Data_Sel, Q=>Mst_WrData(17) );
Mst_WrData_MuxQ16Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(16), B=>Mst_WrData_Reg(16),
S=>Mst_Data_Sel, Q=>Mst_WrData(16) );
Mst_WrData_MuxQ15Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(15), B=>Mst_WrData_Reg(15),
S=>Mst_Data_Sel, Q=>Mst_WrData(15) );
Mst_WrData_MuxQ14Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(14), B=>Mst_WrData_Reg(14),
S=>Mst_Data_Sel, Q=>Mst_WrData(14) );
Mst_WrData_MuxQ13Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(13), B=>Mst_WrData_Reg(13),
S=>Mst_Data_Sel, Q=>Mst_WrData(13) );
Mst_WrData_MuxQ12Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(12), B=>Mst_WrData_Reg(12),
S=>Mst_Data_Sel, Q=>Mst_WrData(12) );
Mst_WrData_MuxQ11Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(11), B=>Mst_WrData_Reg(11),
S=>Mst_Data_Sel, Q=>Mst_WrData(11) );
Mst_WrData_MuxQ10Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(10), B=>Mst_WrData_Reg(10),
S=>Mst_Data_Sel, Q=>Mst_WrData(10) );
Mst_WrData_MuxQ9Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(9), B=>Mst_WrData_Reg(9),
S=>Mst_Data_Sel, Q=>Mst_WrData(9) );
Mst_WrData_MuxQ8Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(8), B=>Mst_WrData_Reg(8),
S=>Mst_Data_Sel, Q=>Mst_WrData(8) );
Mst_WrData_MuxQ7Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(7), B=>Mst_WrData_Reg(7),
S=>Mst_Data_Sel, Q=>Mst_WrData(7) );
Mst_WrData_MuxQ6Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(6), B=>Mst_WrData_Reg(6),
S=>Mst_Data_Sel, Q=>Mst_WrData(6) );
Mst_WrData_MuxQ5Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(5), B=>Mst_WrData_Reg(5),
S=>Mst_Data_Sel, Q=>Mst_WrData(5) );
Mst_WrData_MuxQ4Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(4), B=>Mst_WrData_Reg(4),
S=>Mst_Data_Sel, Q=>Mst_WrData(4) );
Mst_WrData_MuxQ3Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(3), B=>Mst_WrData_Reg(3),
S=>Mst_Data_Sel, Q=>Mst_WrData(3) );
Mst_WrData_MuxQ2Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(2), B=>Mst_WrData_Reg(2),
S=>Mst_Data_Sel, Q=>Mst_WrData(2) );
Mst_WrData_MuxQ1Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(1), B=>Mst_WrData_Reg(1),
S=>Mst_Data_Sel, Q=>Mst_WrData(1) );
Mst_WrData_MuxQ0Q : MUX2X0
Port Map ( A=>Mst_WrData_FIFO(0), B=>Mst_WrData_Reg(0),
S=>Mst_Data_Sel, Q=>Mst_WrData(0) );
mxledQ7Q : MUX2X0
Port Map ( A=>WrBuff_full, B=>ledout(7), S=>ledcntrl, Q=>mxledo(7) );
mxledQ6Q : MUX2X0
Port Map ( A=>WrBuff_empty, B=>ledout(6), S=>ledcntrl,
Q=>mxledo(6) );
mxledQ5Q : MUX2X0
Port Map ( A=>RdBuff_full, B=>ledout(5), S=>ledcntrl, Q=>mxledo(5) );
mxledQ4Q : MUX2X0
Port Map ( A=>Rdbuff_empty, B=>ledout(4), S=>ledcntrl,
Q=>mxledo(4) );
mxledQ3Q : MUX2X0
Port Map ( A=>orn_in, B=>ledout(3), S=>ledcntrl, Q=>mxledo(3) );
mxledQ2Q : MUX2X0
Port Map ( A=>paen_in, B=>ledout(2), S=>ledcntrl, Q=>mxledo(2) );
mxledQ1Q : MUX2X0
Port Map ( A=>pafn_in, B=>ledout(1), S=>ledcntrl, Q=>mxledo(1) );
mxledQ0Q : MUX2X0
Port Map ( A=>irn_in, B=>ledout(0), S=>ledcntrl, Q=>mxledo(0) );
I_137 : DMAREGRD
Port Map ( adr(9 downto 2)=>ADR(9 downto 2),
CBE(3 downto 0)=>Usr_CBE(3 downto 0), clk=>PCI_clock,
clr=>PCI_reset, DMARdEn=>DMARdEn, DMAWrEn=>DMAWrEn,
IncrAddr=>Usr_Adr_Inc, LoadAddr=>Usr_Adr_Valid,
PCI_data(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
PCI_Wr=>N_9, clkspd(2)=>s1en, clkspd(1)=>s0en,
clkspd(0)=>s1s0,
dataout(31 downto 0)=>Usr_RdDataIn(31 downto 0),
led(7 downto 0)=>ledout(7 downto 0), ledcntrl=>ledcntrl,
Usr_Rdy=>Usr_Rdy, Usr_Stop=>Prog_Stop );
I_134 : FIFOCONT
Port Map ( clk=>local_clock, clr=>loc_sync_reset,
idt_fifo_ae_n=>paen_in, idt_fifo_af_n=>pafn_in,
idt_fifo_empty=>orn_in, idt_fifo_full=>irn_in,
rbuff_ae=>RdBuff_almost_empty,
rbuff_empty=>Rdbuff_empty, wbuff_af=>WrBuff_almost_full,
wbuff_full=>WrBuff_full, fpga_oe=>fpga_oe,
idt_fifo_oe_n=>fifo_oe_n, ldn=>ldn, re=>re_out,
re_dly=>re_dly, we=>we_out, we_int=>we_int );
I_124 : DFFP
Port Map ( CLK=>local_clock, D=>N_15, PRE=>PCI_reset, Q=>N_16 );
I149 : DFFP
Port Map ( CLK=>PCI_clock, D=>Rdbuff_empty, PRE=>local_reset,
Q=>RdBuff_empty_sync );
I_114 : INITFLGS
Port Map ( clk=>PCI_clock, clr=>local_reset,
datain(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
pushin=>N_7,
dataout(31 downto 0)=>RdBuff_mux(31 downto 0),
push=>N_1 );
I219 : INV
Port Map ( A=>N_16, Q=>N_19 );
ledinvQ7Q : INV
Port Map ( A=>mxledo(7), Q=>mxledoi(7) );
ledinvQ6Q : INV
Port Map ( A=>mxledo(6), Q=>mxledoi(6) );
ledinvQ5Q : INV
Port Map ( A=>mxledo(5), Q=>mxledoi(5) );
ledinvQ4Q : INV
Port Map ( A=>mxledo(4), Q=>mxledoi(4) );
ledinvQ3Q : INV
Port Map ( A=>mxledo(3), Q=>mxledoi(3) );
ledinvQ2Q : INV
Port Map ( A=>mxledo(2), Q=>mxledoi(2) );
ledinvQ1Q : INV
Port Map ( A=>mxledo(1), Q=>mxledoi(1) );
ledinvQ0Q : INV
Port Map ( A=>mxledo(0), Q=>mxledoi(0) );
I_129 : INV
Port Map ( A=>LocalEn, Q=>N_15 );
I212 : INV
Port Map ( A=>re_out, Q=>N_17 );
I213 : INV
Port Map ( A=>we_out, Q=>N_18 );
I146 : INV
Port Map ( A=>WrBuff_full, Q=>WrBuff_fullN );
I_80 : INV
Port Map ( A=>RdBuff_full, Q=>RdBuff_fullN );
I_81 : INV
Port Map ( A=>WrBuff_empty, Q=>WrBuff_emptyN );
DMA : DMACNTRL
Port Map ( BusMstEn=>Cfg_CmdReg(2), IncrAddr=>Usr_Adr_Inc,
LastWr=>WrBuff_almost_empty,
Mst_BE_FIFO(3 downto 0)=>Mst_BE_FIFO(3 downto 0),
Mst_RdBurst_Done=>Mst_RdBurst_Done,
Mst_RdData_Valid=>Mst_RdData_Valid,
Mst_Tabort_Det=>Mst_Tabort_Det, Mst_TTO_Det=>DMA_Error,
Mst_WrBurst_Done=>Mst_WrBurst_Done,
Mst_WrData_Rdy=>Mst_WrData_Rdy,
Mst_Xfer_D1=>Mst_Xfer_D1, PCI_clk=>PCI_clock,
PCI_reset=>PCI_reset, RdRdy=>RdBuff_empty_sync,
Usr_Ad(9 downto 2)=>ADR(9 downto 2),
Usr_CBE(3 downto 0)=>Usr_CBE(3 downto 0),
Usr_RdDataIn(31 downto 0)=>Usr_RdDataIn(31 downto 0),
Usr_WrData(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
Usr_Write=>Usr_Write, WrRdy=>WrBuff_emptyN,
BEfifo=>BEfifo, DMARdEn=>DMARdEn, DMAWrEn=>DMAWrEn,
LocalEn=>LocalEn,
Mst_BE(3 downto 0)=>Mst_BE(3 downto 0),
Mst_BE_Sel=>Mst_BE_Sel, Mst_Burst_Req=>Mst_Burst_Req,
Mst_Data_Sel=>Mst_Data_Sel, Mst_LatCntEn=>Mst_LatCntEn,
Mst_One_Read=>Mst_One_Read,
Mst_Rd_Term_Sel=>Mst_Rd_Term_Sel,
Mst_RdAd(31 downto 0)=>Mst_RdAd(31 downto 0),
Mst_Two_Reads=>Mst_Two_Reads,
Mst_WrAd(31 downto 0)=>Mst_WrAd(31 downto 0),
Mst_WrData_Valid=>Mst_WrData_Valid,
MstRdAd_Sel=>Usr_MstRdAd_Sel,
MstWrAd_Sel=>Usr_MstWrAd_Sel,
PCI_Cmd(3 downto 0)=>PCI_Cmd(3 downto 0),
Usr_RdData(31 downto 0)=>Usr_RdData(31 downto 0),
WD_Reg(31 downto 0)=>Mst_WrData_Reg(31 downto 0) );
end SCHEMATIC;
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