pci5632_280.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

             Usr_Addr_WrData : Out   STD_LOGIC_VECTOR  (31 downto 0);
             Usr_Adr_Inc : Out   STD_LOGIC;
             Usr_Adr_Valid : Out   STD_LOGIC;
             Usr_CBE : Out   STD_LOGIC_VECTOR  (3 downto 0);
             Usr_DEVSEL : Out   STD_LOGIC;
             Usr_Last_Cycle_D1 : Out   STD_LOGIC;
             Usr_Read : Out   STD_LOGIC;
             Usr_STOPO : Out   STD_LOGIC;
             Usr_TRDY : Out   STD_LOGIC;
             Usr_Write : Out   STD_LOGIC );
   end component;

   component TRIPAD_25UM
      Port (       A : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   P : Out   STD_LOGIC );
   end component;

   component GCLKBUFF_25UM
      Port (       A : In    STD_LOGIC;
                   Z : Out   STD_LOGIC );
   end component;

   component BIPADIFF_25UM
      Port (      A2 : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
               FFCLK : In    STD_LOGIC;
               FFCLR : In    STD_LOGIC;
                FFEN : In    STD_LOGIC;
                   P : InOut STD_LOGIC;
                 FFQ : Out   STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component CKPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component OUTPAD_25UM
      Port (       A : In    STD_LOGIC;
                   P : Out   STD_LOGIC );
   end component;

   component INPADFF_25UM
      Port (   FFCLK : In    STD_LOGIC;
               FFCLR : In    STD_LOGIC;
                FFEN : In    STD_LOGIC;
                   P : In    STD_LOGIC;
                 FFQ : Out   STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I2
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFF
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND4I3
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFFE
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component OR3I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component OR2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component MUX2X0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   S : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DMAREGRD
      Port (     adr : In    STD_LOGIC_VECTOR  (9 downto 2);
                 CBE : In    STD_LOGIC_VECTOR  (3 downto 0);
                 clk : In    STD_LOGIC;
                 clr : In    STD_LOGIC;
             DMARdEn : In    STD_LOGIC;
             DMAWrEn : In    STD_LOGIC;
             IncrAddr : In    STD_LOGIC;
             LoadAddr : In    STD_LOGIC;
             PCI_data : In    STD_LOGIC_VECTOR  (31 downto 0);
              PCI_Wr : In    STD_LOGIC;
              clkspd : Out   STD_LOGIC_VECTOR  (2 downto 0);
             dataout : Out   STD_LOGIC_VECTOR  (31 downto 0);
                 led : Out   STD_LOGIC_VECTOR  (7 downto 0);
             ledcntrl : Out   STD_LOGIC;
             Usr_Rdy : Out   STD_LOGIC;
             Usr_Stop : Out   STD_LOGIC );
   end component;

   component FIFOCONT
      Port (     clk : In    STD_LOGIC;
                 clr : In    STD_LOGIC;
             idt_fifo_ae_n : In    STD_LOGIC;
             idt_fifo_af_n : In    STD_LOGIC;
             idt_fifo_empty : In    STD_LOGIC;
             idt_fifo_full : In    STD_LOGIC;
             rbuff_ae : In    STD_LOGIC;
             rbuff_empty : In    STD_LOGIC;
             wbuff_af : In    STD_LOGIC;
             wbuff_full : In    STD_LOGIC;
             fpga_oe : Out   STD_LOGIC;
             idt_fifo_oe_n : Out   STD_LOGIC;
                 ldn : Out   STD_LOGIC;
                  re : Out   STD_LOGIC;
              re_dly : Out   STD_LOGIC;
                  we : Out   STD_LOGIC;
              we_int : Out   STD_LOGIC );
   end component;

   component DFFP
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component INITFLGS
      Port (     clk : In    STD_LOGIC;
                 clr : In    STD_LOGIC;
              datain : In    STD_LOGIC_VECTOR  (31 downto 0);
              pushin : In    STD_LOGIC;
             dataout : Out   STD_LOGIC_VECTOR  (31 downto 0);
                push : Out   STD_LOGIC );
   end component;

   component INV
      Port (       A : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DMACNTRL
      Port ( BusMstEn : In    STD_LOGIC;
             IncrAddr : In    STD_LOGIC;
              LastWr : In    STD_LOGIC;
             Mst_BE_FIFO : In    STD_LOGIC_VECTOR  (3 downto 0);
             Mst_RdBurst_Done : In    STD_LOGIC;
             Mst_RdData_Valid : In    STD_LOGIC;
             Mst_Tabort_Det : In    STD_LOGIC;
             Mst_TTO_Det : In    STD_LOGIC;
             Mst_WrBurst_Done : In    STD_LOGIC;
             Mst_WrData_Rdy : In    STD_LOGIC;
             Mst_Xfer_D1 : In    STD_LOGIC;
             PCI_clk : In    STD_LOGIC;
             PCI_reset : In    STD_LOGIC;
               RdRdy : In    STD_LOGIC;
              Usr_Ad : In    STD_LOGIC_VECTOR  (9 downto 2);
             Usr_CBE : In    STD_LOGIC_VECTOR  (3 downto 0);
             Usr_RdDataIn : In    STD_LOGIC_VECTOR  (31 downto 0);
             Usr_WrData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Usr_Write : In    STD_LOGIC;
               WrRdy : In    STD_LOGIC;
              BEfifo : Out   STD_LOGIC;
             DMARdEn : Out   STD_LOGIC;
             DMAWrEn : Out   STD_LOGIC;
             LocalEn : Out   STD_LOGIC;
              Mst_BE : Out   STD_LOGIC_VECTOR  (3 downto 0);
             Mst_BE_Sel : Out   STD_LOGIC;
             Mst_Burst_Req : Out   STD_LOGIC;
             Mst_Data_Sel : Out   STD_LOGIC;
             Mst_LatCntEn : Out   STD_LOGIC;
             Mst_One_Read : Out   STD_LOGIC;
             Mst_Rd_Term_Sel : Out   STD_LOGIC;
             Mst_RdAd : Out   STD_LOGIC_VECTOR  (31 downto 0);
             Mst_Two_Reads : Out   STD_LOGIC;
             Mst_WrAd : Out   STD_LOGIC_VECTOR  (31 downto 0);
             Mst_WrData_Valid : Out   STD_LOGIC;
             MstRdAd_Sel : Out   STD_LOGIC;
             MstWrAd_Sel : Out   STD_LOGIC;
             PCI_Cmd : Out   STD_LOGIC_VECTOR  (3 downto 0);
             Usr_RdData : Out   STD_LOGIC_VECTOR  (31 downto 0);
              WD_Reg : Out   STD_LOGIC_VECTOR  (31 downto 0) );
   end component;

begin


   REQN <= REQN_DUMMY;
   SERRN <= SERRN_DUMMY;
   ren <= ren_DUMMY;
   oe <= oe_DUMMY;
   wen <= wen_DUMMY;
   ld <= ld_DUMMY;
   led(7 downto 0) <= led_DUMMY(7 downto 0);
   INTAN <= INTAN_DUMMY;
   mrs <= mrs_DUMMY;
   I220 : CFGTADDR_5632_280
      Port Map ( CBE(3 downto 0)=>Usr_CBE(3 downto 0),
                 Cfg_Write=>Cfg_Write, IncrAddr=>Usr_Adr_Inc,
                 LoadAddr=>Usr_Adr_Valid, MstPERR_Det=>Cfg_MstPERR_Det,
                 MstSC=>MstSC, PCI_clock=>PCI_clock,
                 PCI_reset=>PCI_reset, PERR_Det=>Cfg_PERR_Det,
                 SERR_Sig=>Cfg_SERR_Sig, Tabort_Det=>Mst_Tabort_Det,
                 TTO_Det=>Mst_TTO_Det,
                 WrData(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
                 Addr_Hit=>Usr_Select,
                 CacheLineSizeReg(7 downto 2)=>Cfg_CacheLineSize(7 downto 2),
                 CfgData(31 downto 0)=>Cfg_RdData(31 downto 0),
                 CmdReg(15 downto 0)=>Cfg_CmdReg(15 downto 0),
                 LatTimerReg(7 downto 0)=>Cfg_LatCnt(7 downto 0),
                 Usr_RdCmd=>Usr_RdDecode, Usr_Stop=>Cfg_Stop,
                 Usr_WrCmd=>Usr_WrDecode,
                 UsrAddr(9 downto 0)=>ADR(9 downto 0) );
   I216 : F128X4_25UM
      Port Map ( clk=>PCI_clock,
                 din(3 downto 0)=>Usr_Addr_WrData(3 downto 0),
                 pop=>BEFIFO_pop, push=>BEfifo, rst=>PCI_reset,
                 dout(3 downto 0)=>Mst_BE_FIFO(3 downto 0),
                 emptyn=>BEFIFO_emptyn, fulln=>BEFIFO_fulln );
   Rdbuff : F32A32_25UM
      Port Map ( din(31 downto 0)=>RdBuff_mux(31 downto 0), pop=>we_int,
                 push=>N_1, rclk=>local_clock, rrst=>loc_sync_reset,
                 wclk=>PCI_clock, wrst=>local_reset,
                 almostempty=>RdBuff_almost_empty, almostfull=>open,
                 dout(31 downto 0)=>RdBuff_out(31 downto 0),
                 empty=>Rdbuff_empty, full=>RdBuff_full );
   WrBuff : F32A32_25UM
      Port Map ( din(31 downto 0)=>WrBuff_in(31 downto 0), pop=>N_6,
                 push=>re_dly, rclk=>PCI_clock, rrst=>local_reset,
                 wclk=>local_clock, wrst=>loc_sync_reset,
                 almostempty=>WrBuff_almost_empty,
                 almostfull=>WrBuff_almost_full,
                 dout(31 downto 0)=>Mst_WrData_FIFO(31 downto 0),
                 empty=>WrBuff_empty, full=>WrBuff_full );
   I214 : PCI32_25UM
      Port Map ( Cfg_CacheLineSize(7 downto 2)=>Cfg_CacheLineSize(7 downto 2),
                 Cfg_CmdReg3=>Cfg_CmdReg(3), Cfg_CmdReg4=>Cfg_CmdReg(4),
                 Cfg_CmdReg6=>Cfg_CmdReg(6), Cfg_CmdReg8=>Cfg_CmdReg(8),
                 Cfg_LatCnt(7 downto 0)=>Cfg_LatCnt(7 downto 0),
                 Cfg_RdData(31 downto 0)=>Cfg_RdData(31 downto 0),
                 CLK=>CLK, Flush_FIFO=>GND, GNTN=>GNTN, IDSEL=>IDSEL,
                 Mst_BE(3 downto 0)=>Mst_BE(3 downto 0),
                 Mst_BE_Sel=>Mst_BE_Sel, Mst_Burst_Req=>Mst_Burst_Req,
                 Mst_LatCntEn=>Mst_LatCntEn, Mst_One_Read=>Mst_One_Read,
                 Mst_Rd_Term_Sel=>Mst_Rd_Term_Sel,
                 Mst_RdAd(31 downto 0)=>Mst_RdAd(31 downto 0),
                 Mst_Two_Reads=>Mst_Two_Reads,
                 Mst_WrAd(31 downto 0)=>Mst_WrAd(31 downto 0),
                 Mst_WrData(31 downto 0)=>Mst_WrData(31 downto 0),
                 Mst_WrData_Valid=>Mst_WrData_Valid,
                 PCI_Cmd(3 downto 0)=>PCI_Cmd(3 downto 0), RSTN=>RSTN,
                 Usr_Abort=>GND, Usr_MstRdAd_Sel=>Usr_MstRdAd_Sel,
                 Usr_MstWrAd_Sel=>Usr_MstWrAd_Sel,
                 Usr_RdData(31 downto 0)=>Usr_RdData(31 downto 0),
                 Usr_RdDecode=>Usr_RdDecode, Usr_Rdy=>Usr_Rdy,
                 Usr_Select=>Usr_Select, Usr_Stop=>Usr_Stop,
                 Usr_WrDecode=>Usr_WrDecode,
                 AD(31 downto 0)=>AD(31 downto 0),
                 CBEN(3 downto 0)=>CBEN(3 downto 0), DEVSELN=>DEVSELN,
                 FRAMEN=>FRAMEN, IRDYN=>IRDYN, PAR=>PAR, PERRN=>PERRN,
                 STOPN=>STOPN, TRDYN=>TRDYN,
                 Cfg_MstPERR_Det=>Cfg_MstPERR_Det,
                 Cfg_PERR_Det=>Cfg_PERR_Det, Cfg_Read=>open,
                 Cfg_SERR_Sig=>Cfg_SERR_Sig, Cfg_Write=>Cfg_Write,
                 Mst_IRDYN=>open, Mst_Last_Cycle=>open,
                 Mst_RdBurst_Done=>Mst_RdBurst_Done,
                 Mst_RdData_Valid=>Mst_RdData_Valid, Mst_REQN=>open,
                 Mst_Tabort_Det=>Mst_Tabort_Det,
                 Mst_TTO_Det=>Mst_TTO_Det,
                 Mst_WrBurst_Done=>Mst_WrBurst_Done,
                 Mst_WrData_Rdy=>Mst_WrData_Rdy,
                 Mst_Xfer_D1=>Mst_Xfer_D1, PCI_clock=>PCI_clock,
                 PCI_DEVSELN_D1=>open, PCI_FRAMEN_D1=>open,
                 PCI_GNTN_D1=>open, PCI_IDSEL_D1=>open,
                 PCI_IRDYN_D1=>open, PCI_reset=>PCI_reset,
                 PCI_STOPN_D1=>open, PCI_TRDYN_D1=>open,
                 REQN=>REQN_DUMMY, SERRN=>SERRN_DUMMY,
                 Usr_Addr_WrData(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
                 Usr_Adr_Inc=>Usr_Adr_Inc, Usr_Adr_Valid=>Usr_Adr_Valid,
                 Usr_CBE(3 downto 0)=>Usr_CBE(3 downto 0),
                 Usr_DEVSEL=>open, Usr_Last_Cycle_D1=>Usr_Last_Cycle_D1,
                 Usr_Read=>open, Usr_STOPO=>open, Usr_TRDY=>open,
                 Usr_Write=>Usr_Write );
   I170 : TRIPAD_25UM
      Port Map ( A=>VCC, EN=>GND, P=>INTAN_DUMMY );
   I215 : GCLKBUFF_25UM
      Port Map ( A=>fpga_oe, Z=>N_10 );
   I187 : GCLKBUFF_25UM
      Port Map ( A=>N_16, Z=>loc_sync_reset );
   I188 : GCLKBUFF_25UM
      Port Map ( A=>N_15, Z=>local_reset );
   ladpadsQ31Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(31), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(31),
                 FFQ=>WrBuff_in(31), Q=>WrD(31) );
   ladpadsQ30Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(30), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(30),
                 FFQ=>WrBuff_in(30), Q=>WrD(30) );
   ladpadsQ29Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(29), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(29),
                 FFQ=>WrBuff_in(29), Q=>WrD(29) );
   ladpadsQ28Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(28), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(28),
                 FFQ=>WrBuff_in(28), Q=>WrD(28) );
   ladpadsQ27Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(27), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(27),
                 FFQ=>WrBuff_in(27), Q=>WrD(27) );
   ladpadsQ26Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(26), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(26),
                 FFQ=>WrBuff_in(26), Q=>WrD(26) );
   ladpadsQ25Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(25), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(25),
                 FFQ=>WrBuff_in(25), Q=>WrD(25) );
   ladpadsQ24Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(24), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(24),
                 FFQ=>WrBuff_in(24), Q=>WrD(24) );
   ladpadsQ23Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(23), EN=>N_10, FFCLK=>local_clock,
                 FFCLR=>loc_sync_reset, FFEN=>N_12, P=>lad(23),
                 FFQ=>WrBuff_in(23), Q=>WrD(23) );
   ladpadsQ22Q : BIPADIFF_25UM
      Port Map ( A2=>RdBuff_out(22), EN=>N_10, FFCLK=>local_clock,