pci5632_280.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

   component OR2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component ECOMP5
      Port (       A : In    STD_LOGIC_VECTOR  (4 downto 0);
                   B : In    STD_LOGIC_VECTOR  (4 downto 0);
                  EQ : Out   STD_LOGIC );
   end component;

begin


   almostempty <= almostempty_DUMMY;
   almostfull <= almostfull_DUMMY;
   dout(31 downto 0) <= dout_DUMMY(31 downto 0);
   empty <= empty_DUMMY;
   full <= full_DUMMY;
   I137 : R128X32_25UM
      Port Map ( ra(6)=>gnd, ra(5)=>gnd,
                 ra(4 downto 0)=>Raddr1(4 downto 0), rclk=>rclk,
                 re=>N_11, wa(6)=>gnd, wa(5)=>gnd,
                 wa(4 downto 0)=>Waddr0(4 downto 0), wclk=>wclk,
                 wd(31 downto 0)=>din(31 downto 0), we=>N_4,
                 rd(31 downto 0)=>dout_DUMMY(31 downto 0) );
   I135 : AFIFOFLG
      Port Map ( clk=>wclk, holdoff=>gnd, one=>minus1, reset=>wrst,
                 rw=>push, set=>gnd, two=>minus2, zero=>zero,
                 almost_on=>almostfull_DUMMY, flag_on=>full_DUMMY );
   I136 : AFIFOFLG
      Port Map ( clk=>rclk, holdoff=>N_9, one=>plus1, reset=>gnd,
                 rw=>pop, set=>rrst, two=>plus2, zero=>zero,
                 almost_on=>almostempty_DUMMY, flag_on=>empty_DUMMY );
   I_120 : DFFPA
      Port Map ( CLK=>rclk, D=>gnd, S=>rrst, Q=>N_9 );
   I_115 : GCNTE5_0
      Port Map ( CLK=>wclk, CLR=>wrst, EN=>N_4,
                 Q(4 downto 0)=>Waddr0(4 downto 0) );
   I_74 : RGEC5_1R
      Port Map ( CLK=>rclk, CLR=>rrst, D(4 downto 0)=>Raddr2(4 downto 0),
                 EN=>N_11, Q(4 downto 0)=>Raddr1(4 downto 0) );
   I_77 : RGEC5_2
      Port Map ( CLK=>wclk, CLR=>wrst, D(4 downto 0)=>Waddr3(4 downto 0),
                 EN=>N_3, Q(4 downto 0)=>Waddr2(4 downto 0) );
   I_78 : GCNTE5_2
      Port Map ( CLK=>rclk, CLR=>rrst, EN=>N_2,
                 Q(4 downto 0)=>Raddr2(4 downto 0) );
   I_79 : GCNTE5_3
      Port Map ( CLK=>wclk, CLR=>wrst, EN=>N_3,
                 Q(4 downto 0)=>Waddr3(4 downto 0) );
   I_128 : OR2I0
      Port Map ( A=>N_10, B=>N_9, Q=>N_2 );
   I_45 : OR2I0
      Port Map ( A=>N_10, B=>N_9, Q=>N_11 );
   I_84 : AND2I1
      Port Map ( A=>push, B=>full_DUMMY, Q=>N_3 );
   I_50 : AND2I1
      Port Map ( A=>push, B=>full_DUMMY, Q=>N_4 );
   I_69 : AND2I1
      Port Map ( A=>pop, B=>empty_DUMMY, Q=>N_10 );
   I_26 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr0(4 downto 0),
                 B(4 downto 0)=>Raddr2(4 downto 0), EQ=>plus2 );
   I_19 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr0(4 downto 0),
                 B(4 downto 0)=>Raddr1(4 downto 0), EQ=>plus1 );
   I_85 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr2(4 downto 0),
                 B(4 downto 0)=>Raddr1(4 downto 0), EQ=>minus1 );
   I_18 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr3(4 downto 0),
                 B(4 downto 0)=>Raddr1(4 downto 0), EQ=>minus2 );
   I_17 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr2(4 downto 0),
                 B(4 downto 0)=>Raddr2(4 downto 0), EQ=>zero );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE.all;

entity pci5632_280 is
      Port (   pae_n : In    STD_LOGIC;
               paf_n : In    STD_LOGIC;
                REQN : Out   STD_LOGIC;
               SERRN : Out   STD_LOGIC;
               PERRN : InOut STD_LOGIC;
                 PAR : InOut STD_LOGIC;
                GNTN : In    STD_LOGIC;
               STOPN : InOut STD_LOGIC;
               IDSEL : In    STD_LOGIC;
             DEVSELN : InOut STD_LOGIC;
                RSTN : In    STD_LOGIC;
               TRDYN : InOut STD_LOGIC;
                 CLK : In    STD_LOGIC;
               IRDYN : InOut STD_LOGIC;
              FRAMEN : InOut STD_LOGIC;
                CBEN : InOut STD_LOGIC_VECTOR (3 downto 0);
                  AD : InOut STD_LOGIC_VECTOR (31 downto 0);
                lclk : In    STD_LOGIC;
                 ren : Out   STD_LOGIC;
                  oe : Out   STD_LOGIC;
                 wen : Out   STD_LOGIC;
                  ld : Out   STD_LOGIC;
                 lad : InOut STD_LOGIC_VECTOR (31 downto 0);
                 led : Out   STD_LOGIC_VECTOR (7 downto 0);
               INTAN : Out   STD_LOGIC;
                 mrs : Out   STD_LOGIC;
                or_n : In    STD_LOGIC;
                ir_n : In    STD_LOGIC );
end pci5632_280;


architecture SCHEMATIC of pci5632_280 is

   signal  Usr_CBE : STD_LOGIC_VECTOR (3 downto 0);
   signal Cfg_RdData : STD_LOGIC_VECTOR (31 downto 0);
   signal Cfg_LatCnt : STD_LOGIC_VECTOR (7 downto 0);
   signal Usr_RdData : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_RdAd : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_WrAd : STD_LOGIC_VECTOR (31 downto 0);
   signal RdBuff_out : STD_LOGIC_VECTOR (31 downto 0);
   signal WrBuff_in : STD_LOGIC_VECTOR (31 downto 0);
   signal RdBuff_mux : STD_LOGIC_VECTOR (31 downto 0);
   signal      ADR : STD_LOGIC_VECTOR (9 downto 0);
   signal Cfg_CmdReg : STD_LOGIC_VECTOR (15 downto 0);
   signal   ledout : STD_LOGIC_VECTOR (7 downto 0);
   signal Usr_Addr_WrData : STD_LOGIC_VECTOR (31 downto 0);
   signal   Mst_BE : STD_LOGIC_VECTOR (3 downto 0);
   signal  PCI_Cmd : STD_LOGIC_VECTOR (3 downto 0);
   signal Mst_BE_FIFO : STD_LOGIC_VECTOR (3 downto 0);
   signal Usr_RdDataIn : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_WrData_Reg : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_WrData_FIFO : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_WrData : STD_LOGIC_VECTOR (31 downto 0);
   signal      WrD : STD_LOGIC_VECTOR (31 downto 0);
   signal Cfg_CacheLineSize : STD_LOGIC_VECTOR (7 downto 2);
   signal  mxledoi : STD_LOGIC_VECTOR (7 downto 0);
   signal   mxledo : STD_LOGIC_VECTOR (7 downto 0);
   signal     N_19 : STD_LOGIC;
   signal     N_15 : STD_LOGIC;
   signal     N_16 : STD_LOGIC;
   signal     N_17 : STD_LOGIC;
   signal     N_18 : STD_LOGIC;
   signal     N_10 : STD_LOGIC;
   signal     N_11 : STD_LOGIC;
   signal     N_12 : STD_LOGIC;
   signal Mst_LatCntEn : STD_LOGIC;
   signal Usr_Last_Cycle_D1 : STD_LOGIC;
   signal Usr_Stop : STD_LOGIC;
   signal      N_9 : STD_LOGIC;
   signal    MstSC : STD_LOGIC;
   signal      N_8 : STD_LOGIC;
   signal Mst_Data_Sel : STD_LOGIC;
   signal      N_7 : STD_LOGIC;
   signal      N_6 : STD_LOGIC;
   signal Mst_BE_Sel : STD_LOGIC;
   signal BEFIFO_pop : STD_LOGIC;
   signal      N_5 : STD_LOGIC;
   signal BEFIFO_fulln : STD_LOGIC;
   signal BEFIFO_emptyn : STD_LOGIC;
   signal   BEfifo : STD_LOGIC;
   signal     s1s0 : STD_LOGIC;
   signal     s0en : STD_LOGIC;
   signal     s1en : STD_LOGIC;
   signal ledcntrl : STD_LOGIC;
   signal Mst_Rd_Term_Sel : STD_LOGIC;
   signal RdBuff_empty_sync : STD_LOGIC;
   signal fifo_oe_n : STD_LOGIC;
   signal   we_out : STD_LOGIC;
   signal      N_4 : STD_LOGIC;
   signal DMA_Error : STD_LOGIC;
   signal WrBuff_fullN : STD_LOGIC;
   signal   re_dly : STD_LOGIC;
   signal   we_int : STD_LOGIC;
   signal Cfg_Stop : STD_LOGIC;
   signal Prog_Stop : STD_LOGIC;
   signal  Usr_Rdy : STD_LOGIC;
   signal RdBuff_fullN : STD_LOGIC;
   signal      N_1 : STD_LOGIC;
	constant 		VCC : STD_LOGIC := '1';
   signal Mst_RdData_Valid : STD_LOGIC;
   signal      ldn : STD_LOGIC;
   signal   re_out : STD_LOGIC;
   signal  DMAWrEn : STD_LOGIC;
   signal  paen_in : STD_LOGIC;
   signal  fpga_oe : STD_LOGIC;
   signal Usr_Write : STD_LOGIC;
   signal  DMARdEn : STD_LOGIC;
   signal Mst_WrData_Valid : STD_LOGIC;
   signal WrBuff_almost_full : STD_LOGIC;
   signal Mst_Xfer_D1 : STD_LOGIC;
   signal Mst_Burst_Req : STD_LOGIC;
   signal Mst_One_Read : STD_LOGIC;
   signal Mst_Two_Reads : STD_LOGIC;
   signal RdBuff_almost_empty : STD_LOGIC;
   signal local_clock : STD_LOGIC;
   signal WrBuff_emptyN : STD_LOGIC;
   signal WrBuff_almost_empty : STD_LOGIC;
   signal Usr_MstRdAd_Sel : STD_LOGIC;
   signal Mst_WrBurst_Done : STD_LOGIC;
   signal Usr_MstWrAd_Sel : STD_LOGIC;
   signal Mst_RdBurst_Done : STD_LOGIC;
   signal Mst_WrData_Rdy : STD_LOGIC;
   signal  LocalEn : STD_LOGIC;
   signal local_reset : STD_LOGIC;
   signal loc_sync_reset : STD_LOGIC;
   signal Cfg_PERR_Det : STD_LOGIC;
   signal Cfg_MstPERR_Det : STD_LOGIC;
   signal Cfg_SERR_Sig : STD_LOGIC;
   signal Mst_Tabort_Det : STD_LOGIC;
   signal Mst_TTO_Det : STD_LOGIC;
   signal   irn_in : STD_LOGIC;
   signal  pafn_in : STD_LOGIC;
   signal   orn_in : STD_LOGIC;
   signal Rdbuff_empty : STD_LOGIC;
   signal RdBuff_full : STD_LOGIC;
   signal WrBuff_empty : STD_LOGIC;
   signal WrBuff_full : STD_LOGIC;
   signal Cfg_Write : STD_LOGIC;
   signal Usr_Adr_Valid : STD_LOGIC;
   signal Usr_Adr_Inc : STD_LOGIC;
   signal Usr_Select : STD_LOGIC;
   signal PCI_reset : STD_LOGIC;
   signal Usr_RdDecode : STD_LOGIC;
   signal PCI_clock : STD_LOGIC;
   signal Usr_WrDecode : STD_LOGIC;
	constant 		GND : STD_LOGIC := '0';
   signal REQN_DUMMY : STD_LOGIC;
   signal SERRN_DUMMY : STD_LOGIC;
   signal ren_DUMMY : STD_LOGIC;
   signal oe_DUMMY : STD_LOGIC;
   signal wen_DUMMY : STD_LOGIC;
   signal ld_DUMMY : STD_LOGIC;
   signal led_DUMMY : STD_LOGIC_VECTOR  (7 downto 0);
   signal INTAN_DUMMY : STD_LOGIC;
   signal mrs_DUMMY : STD_LOGIC;

   component CFGTADDR_5632_280
      Port (     CBE : In    STD_LOGIC_VECTOR  (3 downto 0);
             Cfg_Write : In    STD_LOGIC;
             IncrAddr : In    STD_LOGIC;
             LoadAddr : In    STD_LOGIC;
             MstPERR_Det : In    STD_LOGIC;
               MstSC : In    STD_LOGIC;
             PCI_clock : In    STD_LOGIC;
             PCI_reset : In    STD_LOGIC;
             PERR_Det : In    STD_LOGIC;
             SERR_Sig : In    STD_LOGIC;
             Tabort_Det : In    STD_LOGIC;
             TTO_Det : In    STD_LOGIC;
              WrData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Addr_Hit : Out   STD_LOGIC;
             CacheLineSizeReg : Out   STD_LOGIC_VECTOR  (7 downto 2);
             CfgData : Out   STD_LOGIC_VECTOR  (31 downto 0);
              CmdReg : Out   STD_LOGIC_VECTOR  (15 downto 0);
             LatTimerReg : Out   STD_LOGIC_VECTOR  (7 downto 0);
             Usr_RdCmd : Out   STD_LOGIC;
             Usr_Stop : Out   STD_LOGIC;
             Usr_WrCmd : Out   STD_LOGIC;
             UsrAddr : Out   STD_LOGIC_VECTOR  (9 downto 0) );
   end component;

   component F128X4_25UM
      Port (     clk : In    STD_LOGIC;
                 din : In    STD_LOGIC_VECTOR  (3 downto 0);
                 pop : In    STD_LOGIC;
                push : In    STD_LOGIC;
                 rst : In    STD_LOGIC;
                dout : Out   STD_LOGIC_VECTOR  (3 downto 0);
              emptyn : Out   STD_LOGIC;
               fulln : Out   STD_LOGIC );
   end component;

   component F32A32_25UM
      Port (     din : In    STD_LOGIC_VECTOR  (31 downto 0);
                 pop : In    STD_LOGIC;
                push : In    STD_LOGIC;
                rclk : In    STD_LOGIC;
                rrst : In    STD_LOGIC;
                wclk : In    STD_LOGIC;
                wrst : In    STD_LOGIC;
             almostempty : Out   STD_LOGIC;
             almostfull : Out   STD_LOGIC;
                dout : Out   STD_LOGIC_VECTOR  (31 downto 0);
               empty : Out   STD_LOGIC;
                full : Out   STD_LOGIC );
   end component;

   component PCI32_25UM
      Port ( Cfg_CacheLineSize : In    STD_LOGIC_VECTOR  (7 downto 2);
             Cfg_CmdReg3 : In    STD_LOGIC;
             Cfg_CmdReg4 : In    STD_LOGIC;
             Cfg_CmdReg6 : In    STD_LOGIC;
             Cfg_CmdReg8 : In    STD_LOGIC;
             Cfg_LatCnt : In    STD_LOGIC_VECTOR  (7 downto 0);
             Cfg_RdData : In    STD_LOGIC_VECTOR  (31 downto 0);
                 CLK : In    STD_LOGIC;
             Flush_FIFO : In    STD_LOGIC;
                GNTN : In    STD_LOGIC;
               IDSEL : In    STD_LOGIC;
              Mst_BE : In    STD_LOGIC_VECTOR  (3 downto 0);
             Mst_BE_Sel : In    STD_LOGIC;
             Mst_Burst_Req : In    STD_LOGIC;
             Mst_LatCntEn : In    STD_LOGIC;
             Mst_One_Read : In    STD_LOGIC;
             Mst_Rd_Term_Sel : In    STD_LOGIC;
             Mst_RdAd : In    STD_LOGIC_VECTOR  (31 downto 0);
             Mst_Two_Reads : In    STD_LOGIC;
             Mst_WrAd : In    STD_LOGIC_VECTOR  (31 downto 0);
             Mst_WrData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Mst_WrData_Valid : In    STD_LOGIC;
             PCI_Cmd : In    STD_LOGIC_VECTOR  (3 downto 0);
                RSTN : In    STD_LOGIC;
             Usr_Abort : In    STD_LOGIC;
             Usr_MstRdAd_Sel : In    STD_LOGIC;
             Usr_MstWrAd_Sel : In    STD_LOGIC;
             Usr_RdData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Usr_RdDecode : In    STD_LOGIC;
             Usr_Rdy : In    STD_LOGIC;
             Usr_Select : In    STD_LOGIC;
             Usr_Stop : In    STD_LOGIC;
             Usr_WrDecode : In    STD_LOGIC;
                  AD : InOut STD_LOGIC_VECTOR  (31 downto 0);
                CBEN : InOut STD_LOGIC_VECTOR  (3 downto 0);
             DEVSELN : InOut STD_LOGIC;
              FRAMEN : InOut STD_LOGIC;
               IRDYN : InOut STD_LOGIC;
                 PAR : InOut STD_LOGIC;
               PERRN : InOut STD_LOGIC;
               STOPN : InOut STD_LOGIC;
               TRDYN : InOut STD_LOGIC;
             Cfg_MstPERR_Det : Out   STD_LOGIC;
             Cfg_PERR_Det : Out   STD_LOGIC;
             Cfg_Read : Out   STD_LOGIC;
             Cfg_SERR_Sig : Out   STD_LOGIC;
             Cfg_Write : Out   STD_LOGIC;
             Mst_IRDYN : Out   STD_LOGIC;
             Mst_Last_Cycle : Out   STD_LOGIC;
             Mst_RdBurst_Done : Out   STD_LOGIC;
             Mst_RdData_Valid : Out   STD_LOGIC;
             Mst_REQN : Out   STD_LOGIC;
             Mst_Tabort_Det : Out   STD_LOGIC;
             Mst_TTO_Det : Out   STD_LOGIC;
             Mst_WrBurst_Done : Out   STD_LOGIC;
             Mst_WrData_Rdy : Out   STD_LOGIC;
             Mst_Xfer_D1 : Out   STD_LOGIC;
             PCI_clock : Out   STD_LOGIC;
             PCI_DEVSELN_D1 : Out   STD_LOGIC;
             PCI_FRAMEN_D1 : Out   STD_LOGIC;
             PCI_GNTN_D1 : Out   STD_LOGIC;
             PCI_IDSEL_D1 : Out   STD_LOGIC;
             PCI_IRDYN_D1 : Out   STD_LOGIC;
             PCI_reset : Out   STD_LOGIC;
             PCI_STOPN_D1 : Out   STD_LOGIC;
             PCI_TRDYN_D1 : Out   STD_LOGIC;
                REQN : Out   STD_LOGIC;
               SERRN : Out   STD_LOGIC;