pci_cmd_test.tb

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TB 代码 · 共 327 行

--------------------------------------------------------------------------------
--
-- File : pci_cmd_test.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This file tests the capability of QL5332-33/QL5432-33 devices to generate
--	different kinds of PCI transactions. Only memory transactions are tested.
--	 
-- Hierarchy:
--	This file provides a package to be used by pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--	06/26/01		Richard Yuan			1.0
--		- Header added to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library std;
use std.textio.all;

use work.pci_pack.all;
use work.pci_access_package.all;

package pci_cmd_test_package is
  procedure pci_cmd_test (
					  signal address_reg : inout std_logic_vector(63 downto 0);
					  signal data_reg : inout std_logic_vector(63 downto 0);
					  signal target_bar : inout std_logic_vector(63 downto 0);
					  signal master_abort : in std_logic;
					  signal set_master_abort : out std_logic;
					  signal serrn_detected : in std_logic;
					  signal perrn_detected : in std_logic;
					  signal clear_serr : out std_logic;
					  signal clear_disconnect : out std_logic;
					  signal disconnect_detected : in std_logic;
					  signal clear_perr : out std_logic;

                      SIGNAL master1_start_bit : OUT std_logic;
                      SIGNAL master1_done_bit : IN std_logic;
                      SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
                      SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
                      SIGNAL master1_dword_count : OUT integer;
                      SIGNAL master1_initial_data_delay : OUT integer;
                      SIGNAL master1_next_data_delay : OUT integer;
                      SIGNAL master1_bad_parity_phase: OUT integer;
                      SIGNAL master1_m64bit : OUT std_logic;
                      SIGNAL master1_quiet : OUT std_logic;
                      SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
                      SIGNAL data_array : OUT DATA_ARRAY_TYPE;
					  SIGNAL CLK : IN std_logic
                     );

end pci_cmd_test_package;


package body pci_cmd_test_package is

  procedure pci_cmd_test (
					  signal address_reg : inout std_logic_vector(63 downto 0);
					  signal data_reg : inout std_logic_vector(63 downto 0);
					  signal target_bar : inout std_logic_vector(63 downto 0);
					  signal master_abort : in std_logic;
					  signal set_master_abort : out std_logic;
					  signal serrn_detected : in std_logic;
					  signal perrn_detected : in std_logic;
					  signal clear_serr : out std_logic;
					  signal clear_disconnect : out std_logic;
					  signal disconnect_detected : in std_logic;
					  signal clear_perr : out std_logic;

                      SIGNAL master1_start_bit : OUT std_logic;
                      SIGNAL master1_done_bit : IN std_logic;
                      SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
                      SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
                      SIGNAL master1_dword_count : OUT integer;
                      SIGNAL master1_initial_data_delay : OUT integer;
                      SIGNAL master1_next_data_delay : OUT integer;
                      SIGNAL master1_bad_parity_phase: OUT integer;
                      SIGNAL master1_m64bit : OUT std_logic;
                      SIGNAL master1_quiet : OUT std_logic;
                      SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
                      SIGNAL data_array : OUT DATA_ARRAY_TYPE;
					  SIGNAL CLK : IN std_logic
                     ) is

  variable i : integer;
  variable outline : line;


begin

	-- pci_access procedure
	--
	--              address : IN Destination address of access
    --                 data : IN write/expected data for one quadword transactions (see note)
    --          pci_command : IN The PCI Command to be used for the transfer
    --          byte_enable : IN write/expected byte enables for one quadWord transactions (see note)
    --          dword_count : IN The number of dwords to transfer
    --   initial_waitstates : IN waitstates to insert before 1st IRDYN assertion
    --subsequent_waitstates : IN waitstates to insert after each data phase
	--     bad_parity_phase : IN 0 to disable, sets transfer for bad parity assertion
    --                64bit : IN 1 for a 64-bit master, 0 for a 32-bit master
	--                quiet : IN 0 to issue error if target reads don't match expected data
	--            start_bit : OUT signal passed to simulation master
	--             done_bit : IN signal passed from simulation master
	--                 addr : OUT signal passed to simulation master
	--              command : OUT signal passed to simulation master
	--          dword_count : OUT signal passed to simulation master
	--   initial_data_delay : OUT signal passed to simulation master
	--      next_data_delay : OUT signal passed to simulation master
	--     bad_parity_phase : OUT signal passed to simulation master
	--               m64bit : OUT signal passed to simulation master
	--               mquiet : OUT signal passed to simulation master
	--             be_array : OUT array passed to simulation master
	--           data_array : OUT array passed to simulation master
	--                  CLK : IN 
	--
	-- NOTE: For multi-quadword transactions, be_array and data_array must be initialized
	--       with the appropriate write data for writes, or expected data for reads.


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Start of PCI Command test. "));
writeline(output, outline);


-- write 3 dwords to configuration space to set up the master
wait_for_clocks(CLK,4);
data_array(0) <= x"00000156";
data_array(1) <= x"00000000";
data_array(2) <= x"00004000";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";

pci_access(x"0000000000000004",data_reg,CONFIG_WRITE,x"FF",3,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,4);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Read"));
writeline(output, outline);

-- set up a DMA read of 16
data_array(0) <= x"00100010";
data_array(1) <= x"04444400";
data_array(2) <= x"04444000";
-- master read command 3'b011, all byte lanes on, store data in FIFO
data_array(3) <= "01101101" & x"000000";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,50);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Read Line"));
writeline(output, outline);

-- set up a DMA read of 16
data_array(0) <= x"00100010";
data_array(1) <= x"04444400";
data_array(2) <= x"04444000";
-- master read command 3'b111, all byte lanes on, store data in FIFO
data_array(3) <= "01111101" & x"000000";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,50);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Read Multiple"));
writeline(output, outline);

-- set up a DMA read of 16
data_array(0) <= x"00100010";
data_array(1) <= x"04444400";
data_array(2) <= x"04444000";
-- master read command 3'b110, all byte lanes on, store data in FIFO
data_array(3) <= "01111001" & x"000000";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,50);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write"));
writeline(output, outline);

-- set up a DMA write of 16
data_array(0) <= x"00100010";
data_array(1) <= x"04444400";
data_array(2) <= x"04444000";
-- master write command 3'b011, all byte lanes on, write data from FIFO
data_array(3) <= "01000000" & x"00" & "00000001" & x"00";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,50);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write and Invalidate"));
writeline(output, outline);

-- set up a DMA write of 16
data_array(0) <= x"00100010";
data_array(1) <= x"04444400";
data_array(2) <= x"04444000";
-- master write command 3'b111, all byte lanes on, write data from FIFO
data_array(3) <= "01000000" & x"00" & "00011101" & x"00";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,50);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write and Invalidate with enable bit disabled (should use MW instead)"));
writeline(output, outline);

-- disable the MWI enable bit in configuration
-- master module should use Memory Write instead
-- clear the MWI enable bit
pci_access(x"0000000000000004",x"0000000000000146",CONFIG_WRITE,x"FF",1,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,5);

-- set up a DMA write of 16
data_array(0) <= x"00100010";
data_array(1) <= x"04444400";
data_array(2) <= x"04444000";
-- master write command 3'b111, all byte lanes on, write data from FIFO
data_array(3) <= "01000000" & x"00" & "00011101" & x"00";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",4,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,50);

-- set the MWI enable bit
pci_access(x"0000000000000004",x"0000000000000156",CONFIG_WRITE,x"FF",1,1,1,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
wait_for_clocks(CLK,5);


write(outline, string'("["));
write(outline, now);
write(outline, string'("] End of PCI Command test. "));
writeline(output, outline);

end pci_cmd_test;

end package body pci_cmd_test_package;