idt_fifo.tb

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TB 代码 · 共 147 行

--------------------------------------------------------------------------------
--
-- File : idt_fifo.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	IDT FIFO simulation model, present on the PCI RDK board.
--	 
-- Hierarchy:
--	The idt_fifo entity is to be used in pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--	06/26/01		Richard Yuan			1.0
--		- Header added to conform to coding standard.
--
--------------------------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity idt_fifo is
	port (
			lad : inout std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pae_n, paf_n : out std_logic;
			or_n, ir_n : out std_logic;
			hf_n : out std_logic;
			fs : in std_logic;
			fwft : in std_logic;
			ld : in std_logic;
			rt : in std_logic;
			mrs, prs : in std_logic;
			ren, wen : in std_logic;
			oe : in std_logic;
			lclk : in std_logic
		 );
end idt_fifo;

architecture idt_fifo_arch1 of idt_fifo is
	signal RXDATA : std_logic_vector(31 downto 0);
	signal fwpointer, frpointer : integer := 0;
	type fifo_mem is array (4095 downto 0) of std_logic_vector(31 downto 0);
	signal fifo : fifo_mem;
	signal fcounter : integer := 0;
	signal ppointer : integer := 0;
	type partialreg_mem is array (1 downto 0) of integer;
	signal partialreg : partialreg_mem;
	signal or_n_int, ir_n_int : std_logic;

	constant fifo_size : integer := 4096;
	constant OutDlyFIFO : time := 3 ns;

begin

	lad <= RXDATA after OutDlyFIFO when (oe = '0') else (others => 'Z') after OutDlyFIFO;
	or_n <= or_n_int;
	ir_n <= ir_n_int;

    fifo_pointers : process(lclk, mrs, prs) is begin
	    if ((mrs = '0') or (prs = '0')) then
	    	fcounter <= 0;
			frpointer <= 0;
			fwpointer <= 0;
			ppointer <= 0;
			partialreg(0) <= 127;
			partialreg(1) <= 127;
		elsif (lclk'event and lclk='1') then
			if (ren = '0') then
				if (or_n_int = '0') then
					frpointer <= frpointer + 1;
					fcounter <= fcounter - 1;
				end if;
			end if;
			if (wen = '0' and ld = '0') then
				partialreg(ppointer) <= to_integer(unsigned(lad(31 downto 16)));
				ppointer <= ppointer + 1;
			end if;
			if (wen = '0' and ld = '1') then
				fifo(fwpointer) <= lad;
				if (ir_n_int = '0') then
					fwpointer <= fwpointer + 1;
					fcounter <= fcounter + 1;
				end if;
			end if;
		end if;
	end process;



RXDATA <= fifo(frpointer);

    fifo_flags : process (fcounter, mrs, prs) is begin
	    if ((mrs = '0') or (prs = '0')) then
			or_n_int <= '1';
			ir_n_int <= '0';
			hf_n <= '1';
			pae_n <= '0';
			paf_n <= '1';
		else

	        if (fcounter = 0) then
		        or_n_int <= '1';
			else
	            or_n_int <= '0';
	        end if;

	        if (fcounter = (fifo_size - 1)) then 
		        ir_n_int <= '1';
		    else
	            ir_n_int <= '0';
	        end if;

	        if (fcounter > ((fifo_size / 2) - 1)) then
		        hf_n <= '0';
			else
	            hf_n <= '1';
	        end if;

	        if (fcounter <= partialreg(0)) then
		        pae_n <= '0';
			else
	            pae_n <= '1';
	        end if;

	        if (fcounter >= (fifo_size - partialreg(1))) then
		        paf_n <= '0';
			else
	            paf_n <= '1';
	        end if;

		end if;
    end process;


end idt_fifo_arch1;