dma_test.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 74 行

//------------------------------------------------------------------------------
//
// File : dma_test.tf
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed Customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This file sets the clock frequency and then sets up a DMA read and a DMA write
//	transaction.
//	 
// Hierarchy:
//	This file is to be included by pci5(3/4)32_280.tf.
//
// History:	
//	Date	        Author					Version
//	06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


// set up the simulation target wait state response
target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
target_1.VARIABLE_WAITS = 1;       //Enable variable wait lengths (1 or 0)
target_1.MAX_WAITS = 5;            //Max # of wait states inserted in variable waits mode
target_1.MIN_WAITS = 0;            //Min # of wait states inserted in variable waits mode
target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS = 1;     //# of waits to insert before subsequent trdy's
target_1.STOP_ENABLE = 1;
target_1.STOP_COUNT = 3;

// write 3 dwords to configuration space to set up the master

master_2.data_array[0] = 32'h00000006;
master_2.data_array[1] = 32'h00000000;
master_2.data_array[2] = 32'h00004000;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h4,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,3,1,1,1'b0); 

// write the local clock speed to the clock speed register in the master

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000114,local_clock_control,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0); 

CurRxSize = CurRxSize + 13;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
$display ("DMA Size: %d DWORDs", CurRxSize);
DMACtrlReg = 32'hC1000100;
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master

master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,local_clock_control,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0);