initflgs.v

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· Verilog 代码 · 共 57 行

//------------------------------------------------------------------------------
//
// File : initflgs.v
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This block writes two elements to FIFO immediately after reset, which are
//	used to set the partial empty/full flags on the IDT FIFOs.
//
// Hierarchy:
//	This file represents the initflgs block in pci5(3/4)32_280.sch.
//
// History:	
//	Date	        Author					Version
//  06/26/01		Richard Yuan			1.0
//		- Header reorganized to conform to coding standard.
//
//------------------------------------------------------------------------------


module initflgs (clk, clr, pushin, push, datain, dataout);

	input clk, clr, pushin;
	input [31:0] datain;
	output push;
	output [31:0] dataout;
	
	reg pushinit;
	reg select;
	reg [31:0] dataout;

assign push = pushin || pushinit;

always @(posedge clk or posedge clr)
	if (clr) pushinit <= 0;
		else if (~select) pushinit <= 1;
			else pushinit <= 0;

always @(posedge clk or posedge clr)
	if (clr) select <= 0;
		else if (pushinit) select <= 1;

always @(pushinit or datain)
	case (pushinit)
		0: dataout <= datain;
		1: dataout <= 32'h00080008;
		default: dataout <= 32'hxxxxxxxx;
		endcase


endmodule