cardbus_5632.tf
来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 908 行 · 第 1/2 页
TF
908 行
// Protocol checks
reg [15:0] proto_mem [0:4095];
reg [5:0] cur_st,lst_st;
reg [11:0] st_vec;
reg [15:0] eccode;
reg DMA_WR, DMA_RD;
reg FRAME_D1N,GNT_D1N;
initial begin : Monitor_bus
CurRxAddr = 32'h11110000 >> 2;
CurTxAddr = 32'h11110000 >> 2;
// CurTxAddr = 32'h21110000 >> 2; //test for furusawa-san Mst_TTO_Det error condition
CurRxData = InitRxData;
CurTxData = InitTxData;
RxDataCnt = 0;
TxDataCnt = 0;
InhProtoErr = 0;
CurTxSize=0;
CurRxSize=0;
end
initial begin // load proto checker memory
$readmemh("bus_chk.mem",proto_mem);
end
always @(posedge CLK or negedge RSTN) begin : Proto_chk
if (!RSTN) begin
lst_st = 6'b0;
cur_st = 6'b0;
end else begin
lst_st = cur_st;
cur_st = {1'b0,!FRAMEN,!TRDYN,!IRDYN,!DEVSELN,!STOPN};
st_vec = {lst_st,cur_st};
eccode = proto_mem [st_vec];
if (eccode[ERRIDLE])begin
$display("\tIdle protocol error at %d",$time);
if(!InhProtoErr) err_cnt = err_cnt + 1;
end
if (eccode[ERRFRAME])begin
$display("\tFrame protocol error at %d",$time);
if(!InhProtoErr) err_cnt = err_cnt + 1;
end
if (eccode[ERRIRDY]) begin
$display("\tIRdy protocol error or Master Abort Detected at %d",$time);
if(!InhProtoErr) err_cnt = err_cnt + 1;
end
if (eccode[ERRTRDY])begin
$display("\tTRdy protocol error at %d",$time);
if(!InhProtoErr) err_cnt = err_cnt + 1;
end
if (eccode[ERRDEVSEL])begin
$display("\tDevSel protocol error at %d",$time);
if(!InhProtoErr) err_cnt = err_cnt + 1;
end
if (eccode[ERRSTOP])begin
$display("\tStop protocol error at %d",$time);
if(!InhProtoErr) err_cnt = err_cnt + 1;
end
if (~SERRN) begin
$display ("\tSystem Error Detected at %d", $time);
SERR_Detected = 1;
end
if (~PERRN) begin
$display ("\tParity Error Detected at %d", $time);
PERR_Detected = 1;
end
end
end
always @(negedge CLK) begin
#(HalfCyclePCI - 1)
if (!RSTN) begin
transfers <= 0;
disconnects <= 0;
retrys <= 0;
aborts <= 0;
Master_Abort_Detected <= 1;
InCycle <= 0;
end
else begin
if (!IRDYN & !TRDYN) transfers <= transfers + 1;
if (!IRDYN & !STOPN & !TRDYN) begin
disconnects <= disconnects + 1;
Disconnect_Detected <= 1;
end
if (!IRDYN & !STOPN & TRDYN) begin
retrys <= retrys + 1;
Disconnect_Detected <= 1;
end
if (!STOPN & DEVSELN) aborts <= aborts + 1;
if (~FRAMEN) InCycle <= 1;
if (FRAMEN & IRDYN) InCycle <= 0;
if (InCycle & (~TRDYN || ~STOPN || ~DEVSELN)) Master_Abort_Detected <= 0;
end
end
// Primary Simulation Block
// *************************************************************************
//The Standard PCI access is done with the 'target_access' task.
//Variants on this task include: 'target_access_pf_get_data'
// 'target_access_pf_check_burst_size'
// 'target_access_pf'
// 'target_access_hold_req'
// 'target_access_check_burst_size'
// 'target_access_one_piece'
// 'target_access_one_frame'
//
//The parameter list for 'target_access' is:
//
//target_access(address,data,pci_command,byte_enable,
// addr_parity,data_parity,dword_count,
// initial_waitstates,subsequent_waitstates,64bit);
//
//address: Destination address of access
//data : If 1 Quadword or less data is being sent, this value is used as
// the data for the transfer
//pci_command: The Command To Be Issued
//byte_enable: If 1 Quadword or less data is being sent, this value is used
// as the be for the transfer
//The addr_parity and data_parity inputs are currently unused.
//dword_count: The number of dwords to transfer
//initial_waitstates: # of waitstates to insert before asserting IRDYN for the first time.
//subsequent_waitstates: # of waitstates to insert after each data phase completes.
//64bit: A 1 here causes the master to act as a 64 bit device for the transaction.
//A 0 causes the master to act as a 32 bit device.
//
// For all transactions that are larger than 1 Quadword, data is taken from/stored in
// the array 'data_array', and byte enables are taken from the array 'be_array'.
// If such transactions are performed, care must be taken to initialize these arrays
// before starting the transactions.
// *************************************************************************
// loop control variables used in compliance test
reg mem, io, cfg, ia, sc;
reg slower_than_subtractive;
reg single_target_abort, single_retry, single_disconnect;
reg multi_target_abort, multi_retry, multi_disconnect;
reg mrl, mrm;
reg single_parity_error;
// DS
// CTU
reg tb_clkrun_oe, tb_clkrun_n;
assign pad_CCLKRUN_n = tb_clkrun_oe ? tb_clkrun_n : 1'bZ;
// DS
initial begin : SystemInit
mem <= 1'b0;
io <= 1'b0;
cfg <= 1'b0;
ia <= 1'b0;
sc <= 1'b0;
slower_than_subtractive <= 1'b0;
single_target_abort <= 1'b0;
single_retry <= 1'b0;
single_disconnect <= 1'b0;
multi_target_abort <= 1'b0;
multi_retry <= 1'b0;
multi_disconnect <= 1'b0;
mrl <= 1'b0;
mrm <= 1'b0;
single_parity_error <= 1'b0;
CurRxSize = 1;
err_cnt = 0;
DMAReadEnabled = 0;
DMAWriteEnabled = 0;
// added CardBus IP signals
$display("in PCI compliance test, should expect false errors:");
$display("config read x24, get BAR5's values instead of 0");
$display("config read x28, get CIS location instead of 0");
$display("(each of above for 2 times)");
pad_BAM <= 1'b0;
pad_bvd[2:1] <= 2'b00;
pad_clk_resume <= 1'b0;
pad_CBLOCK_n <= 1'b1;
pad_PWM <= 1'b0;
pad_ready <= 1'b0;
pad_wp <= 1'b0;
pad_gwake <= 1'b0;
pad_intr <= 1'b0;
tb_clkrun_oe <= 1'b1;
tb_clkrun_n <= 1'b0;
RSTN <= 1'b1; // No reset at beginning
RSTN <= #1 1'b0; // Assert reset after 1 ns
repeat (20) @(posedge CLK); // Sit in reset for a bit
RSTN <= #1 1'b1; // Go out of reset
repeat (5) @(posedge CLK);
$display("");
// DS added
$display("Setting Base Address 0: %0x, time: %0t",32'h22000000,$time);
master_2.target_access(32'h10,32'hFFFFFFFF,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h10,32'hFFFFFFFF,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h10,32'h22000000,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h10,32'h22000000,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (5) @(posedge CLK);
$display("Setting Base Address 5 (for CIS): %0x, time: %0t",CardBus_BAR,$time);
master_2.target_access(32'h24,32'hFFFFFFFF,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h24,32'hFFFFFFFF,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h24,CardBus_BAR,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h24,CardBus_BAR,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (5) @(posedge CLK);
$display("\nEnabling Memory: %0x, time: %0t",32'h62,$time);
master_2.target_access(32'h4,32'h162,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (5) @(posedge CLK);
$display("Reading rest of BARs: time: %0t",$time);
master_2.target_access(32'h14,32'hFFFFFFFF,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h18,32'hFFFFFFFF,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h1C,32'hFFFFFFFF,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (2) @(posedge CLK);
master_2.target_access(32'h20,32'hFFFFFFFF,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
repeat (5) @(posedge CLK);
$display("Initializing Target Memory");
for (index = 0; index < 18'h3FFFF; index = index+4)
{target_1.MyMemory[index+3],target_1.MyMemory[index+2],target_1.MyMemory[index+1],
target_1.MyMemory[index]} = InitRxData + (index/4);
$display("Target Memory Initialized");
$display("");
repeat (5) @(posedge CLK);
/* repeat (5) @(posedge CLK);
master_2.target_access(32'h0,32'h162,CONFIG_READ,8'hFF,1'b0,1'b0,1,4'h1,4'h1,1'b0);
master_2.be_array[0] = 8'hF1;
master_2.be_array[1] = 8'hF3;
master_2.be_array[2] = 8'hF1;
master_2.be_array[3] = 8'hF3;
master_2.be_array[4] = 8'hF1;
repeat (5) @(posedge CLK);
master_2.target_access(32'h0,32'h162,CONFIG_READ,8'hFF,1'b0,1'b0,5,4'h4,4'h4,1'b0);
master_2.data_array[0] = 32'h00001111;
master_2.data_array[1] = 32'h00001111;
master_2.data_array[2] = 32'h00001111;
master_2.data_array[3] = 32'h00001111;
master_2.data_array[4] = 32'h00001111;
repeat (5) @(posedge CLK);
master_2.target_access(32'h22000200,32'h0,MEM_WRITE,8'hFF,1'b0,1'b0,5,1,1,1'b0);
repeat (5) @(posedge CLK);
master_2.target_access(32'h22000200,32'h0,MEM_READ,8'hFF,1'b0,1'b0,5,2,1,1'b0);
$stop;
*/
// master_2.target_access(32'h3300010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
// CTU test cardbus_wrapper module
`include "cardbus_wrapper.tf"
// test the various PCI commands supported by the master channel
`include "pci_cmd_test.tf"
// test the various byte enable functions
`include "byte_enable_test.tf"
for (j=0;j<6;j=j+1) begin
wait (~DMAReadEnabled && ~DMAWriteEnabled)
DMAReadEnabled = 1;
DMAWriteEnabled = 1;
case (j)
0: begin
local_clock_control = 3'b100; // 28 MHz Local Clock
$display("\n\n%0d) Running Big DMA Test (28 MHz) at %0d",j+1,$time);
`include "dma_test.tf" // reads and writes all configuration registers
end
1: begin
local_clock_control = 3'b110; // 42 MHz Local Clock
$display("\n\n%0d) Running Big DMA Test (42 MHz) at %0d",j+1,$time);
`include "dma_test.tf" // reads and writes all configuration registers
end
2: begin
local_clock_control = 3'b011; // 56 MHz Local Clock
$display("\n\n%0d) Running Big DMA Test (56 MHz) at %0d",j+1,$time);
`include "dma_test.tf" // reads and writes all configuration registers
end
3: begin
local_clock_control = 3'b000; // 70 MHz Local Clock
$display("\n\n%0d) Running Big DMA Test (70 MHz) at %0d",j+1,$time);
`include "dma_test.tf" // reads and writes all configuration registers
end
4: begin
local_clock_control = 3'b010; // 84 MHz Local Clock
$display("\n\n%0d) Running Big DMA Test (84 MHz) at %0d",j+1,$time);
`include "dma_test.tf" // reads and writes all configuration registers
end
5: begin
DMAReadEnabled = 0; // Disable DMA Checking
DMAWriteEnabled = 0; // Disable DMA Checking
// $display("\n\n%0d) Running PCI Compliance Tests at %0d",j+1,$time);
// uncomment the following line for compliantce test target portion
// $display("TARGET COMPLIANCE TESTS PASSED!!! MODIFIED 3 PLACES IN CT_TARGET.TF FOR BAR INFO");
// `include "ct_target.tf"
// uncomment the following line for compliantce test master portion
// $display("SKIPPING MASTER COMPLIANCE TESTS FOR NOW!!!!!!");
// `include "ct_master.tf"
end
endcase
//Check for simulation complete by reading DMA controller enable bits
while (DMAReadEnabled || DMAWriteEnabled) begin
repeat (100) @(posedge CLK); //wait 100 clock cycles
master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
CheckEnables = master_2.data_read[31:0];
if(DMAWriteEnabled) begin
if (CheckEnables[9:8] == 2'b00) begin
$display("DMA write cycles complete at %0d",$time);
repeat (5) @(posedge CLK);
master_2.target_access(32'h22000110,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
PerfCount = master_2.data_read[31:0];
PCIBandwidth = (LastDMASize*132)/(PerfCount);
$display("PCI Bandwidth Measurement = %0f MB/s", PCIBandwidth);
DMAWriteEnabled = 0;
end
if (CheckEnables[9] == 1'b1) begin
$display("DMA write error at %0d",$time);
$display("Resetting Board");
repeat (5) @(posedge CLK); //wait 5 clock cycles
master_2.target_access(32'h2200010C,32'h00000000,MEM_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
DMAWriteEnabled = 0;
end
end
if(DMAReadEnabled) begin
if (CheckEnables[25:24] == 2'b00) begin
$display("DMA read cycles complete at %0d",$time);
DMAReadEnabled = 0;
end
if (CheckEnables[25] == 1'b1) begin
$display("DMA read error at %0d",$time);
$display("Resetting Board");
repeat (5) @(posedge CLK); //wait 5 clock cycles
master_2.target_access(32'h2200010C,32'h00000000,MEM_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
DMAReadEnabled = 0;
end
end
end // while loop
end //for loop
#1000;
$display("\n\n\tTotal Transfers = %d",transfers);
$display("\tTotal Target Disconnects with Data = %d",disconnects);
$display("\tTotal Target Disconnects without Data = %d",retrys);
$display("\tTotal Target Aborts = %d",aborts);
$display("\nEnd of test loop at %0d",$time);
$stop;
end
/*wire [7:0] cnt;
initial begin
@(posedge m.I150.Mst_Rd_Term_Sel);
force m.I150.Mst_WrData_Valid = 1'b1;
force m.I150.Mst_One_Read = 1'b0;
force m.I150.Mst_Two_Reads = 1'b0;
cnt <= m.DMA.Burst_Cnt-1;
@(posedge CLK);
while (cnt) begin
repeat (1) @(posedge CLK);
if (m.I150.Mst_WrData_Rdy) cnt <= cnt-1;
end
release m.Mst_WrData_Valid;
wait (m.I150.Mst_RdBurst_Done);
release m.Mst_One_Read;
release m.Mst_Two_Reads;
end*/
/*initial begin
#5411
force m.I150.Mst_WrData_Valid = 1'b1;
force m.I150.Mst_WrData = 32'h47474747;
#30
release m.I150.Mst_WrData_Valid;
release m.I150.Mst_WrData;
end*/
/*initial begin
#2056
force m.I168.Usr_Abort = 1'b1;
#180
release m.I168.Usr_Abort;
end*/
/*initial begin
#3046
force m.I150.GNTN = 1'b0;
#300
release m.I150.GNTN;
end*/
/*initial begin
#1846
force m.CBEN[3:0] = 4'b1001;
#30
release m.CBEN[3:0];
end*/
/*initial begin
#3736
force m.I150.Mst_Burst_Req = 1'b1;
#300
release m.I150.Mst_Burst_Req;
end*/
/*initial begin
#2656
force m.I168.Usr_Stop = 1'b1;
force m.I168.Usr_Rdy = 1'b1;
#30
release m.I168.Usr_Stop;
release m.I168.Usr_Rdy;
#210
force m.I168.Usr_Stop = 1'b1;
force m.I168.Usr_Rdy = 1'b0;
#30
release m.I168.Usr_Stop;
release m.I168.Usr_Rdy;
#210
force m.I168.Usr_Stop = 1'b1;
force m.I168.Usr_Rdy = 1'b0;
#30
release m.I168.Usr_Stop;
release m.I168.Usr_Rdy;
end*/
endmodule
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