cardbus_5632.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 908 行 · 第 1/2 页

//------------------------------------------------------------------------------
//
// File : cardbus_5632.tf
// Last Modification: May/08/2002
//
// Created In SpDE Version: SpDE 9.3
// Author :      QuickLogic Corporation
// Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	Top-Level Test Bench for the pci5632_280 reference design,
//  converted to CardBus. 
//	
// History:	
//	Date	        Author					Version
//	May/08/2002	Bernhard			        1.0
//		- Reformating of some display messages
//		- Header added to conform to coding standard.
//	08/02/2002	Jens Niemann				1.1
//		- Removed some ports of the Top level Verilog 
//		- because the 5632-280 package has less I/O pins than
//		- the 5432-280
//------------------------------------------------------------------------------


`timescale 1ns/1ns

`include "pci_arb.tf"  //A pci arbitrator
`include "pci_mast.tf" //The external PCI master
`include "pci_tar.tf"  //The external PCI target
`include "cmd_monitor.tf"	// command moniter

module t;

parameter OutDly=11,OutHld=5;
parameter InitRxData = 32'h80018001, InitTxData = 32'h80018001;
parameter OutDlyLocal = 3;

// THE PCI BUS //
tri1 [63:0] #4 AD;
tri1 [7:0] #4 CBEN;
wire #4 FRAMEN;
wire #4 IRDYN;
wire #4 TRDYN;
wire #4 DEVSELN;
wire #4 STOPN;
wire req64_l;
wire ack64_l;
wire #4 PAR;
wire par64;
wire #4 PERRN;
wire #4 SERRN;
wire INTAN;
wire REQN;
wire #4 GNTN; 
wire #4 master_2_req_l;
wire #4 IDSEL;
wire pad_CCLKRUN_n;

// Bus signal pull ups // 
pullup (FRAMEN);
pullup (IRDYN);
pullup (TRDYN);
pullup (DEVSELN);
pullup (STOPN);
pullup (req64_l);
pullup (ack64_l);
pulldown (PAR );
pulldown (par64 );
pullup (PERRN);
pullup (SERRN);
pullup (INTAN);
pullup (REQN);
pullup (master_2_req_l);
pulldown (IDSEL);
pullup (pad_CCLKRUN_n);

// PCI CLOCK AND RESET //
reg CLK;  
reg RSTN;

wire [7:0] cmd_mon;   //command monitor signals 	
wire [7:0] test_type; //command monitor signals	


// PCI COMMAND CODES //
parameter INTERRUPT_ACK  = 4'b0000;
parameter SPECIAL_CYCLE  = 4'b0001;
parameter IO_READ        = 4'b0010;
parameter IO_WRITE       = 4'b0011;
parameter CMD_RESERVED_1 = 4'b0100;
parameter CMD_RESERVED_2 = 4'b0101;
parameter MEM_READ       = 4'b0110;
parameter MEM_WRITE      = 4'b0111;
parameter CMD_RESERVED_3 = 4'b1000;
parameter CMD_RESERVED_4 = 4'b1001;
parameter CONFIG_READ    = 4'b1010;
parameter CONFIG_WRITE   = 4'b1011;
parameter MEM_READ_MULT  = 4'b1100;
parameter DUAL_ADDR      = 4'b1101;
parameter MEM_READ_LINE  = 4'b1110;
parameter MEM_WR_INVALID = 4'b1111;

// DS added for CardBus
parameter	CardBus_BAR = 32'hCB000000;	
parameter	EVENT_OFFSET = 10'h300;
parameter	MASK_OFFSET = 10'h304;
parameter	STATE_OFFSET = 10'h308;
parameter	FORCE_OFFSET = 10'h30C;
parameter 	CIS_OFFSET_0 = 8'h00;
parameter 	CIS_OFFSET_1 = 8'h04;
parameter 	CIS_OFFSET_2 = 8'h08;
parameter 	CIS_OFFSET_3 = 8'h0C;
parameter 	CIS_OFFSET_4 = 8'h10;

// LEDs
wire [7:0] led;	// active low LEDs

// Programmable On-Board Clock Chip
reg lclk;			// on-board clock (20-100 MHz)
wire s0;
wire s1;		// clock speed select
assign s0 = 1'bz;
assign s1 = 1'bz;

// FIFO Access Port (Master Read/Writes)
parameter FIFO_SIZE = 4096;
parameter PARTIAL_FLAG_DEFAULT = 8;
wire [31:0] lad;  // 32 bit data (bidirectional)
reg pae_n, paf_n; // programmable almost empty/full flags (active low)
reg or_n, ir_n;	  // empty/full flags (active low)
reg hf_n;         // half full flag (active low)
wire fs;          // frequency select (not used, tied to GND)
wire fwft;			// first-word-flow-through
wire ld;				// load for almost empty/full flags
wire rt;				// retransmit
wire mrs;
wire prs;		// master reset, partial reset (unused)
assign prs = 1'b1;
wire ren, wen;		// read enable, write enable (both active low)
wire oe;				// output enable for lad[31:0] (active low)
integer fcounter; // fifo status counter
reg [12:0] fwpointer, frpointer; // fifo write and read pointers
reg [31:0] fifo [FIFO_SIZE-1:0]; // FIFO Memory
wire [31:0] RXDATA;
reg ppointer;		// fifo partial flag pointer for writes
reg [15:0] partialreg [1:0]; // FIFO partial flag registers

// Usused PCI Signals
wire intb, intc, intd, sbo, sdone;
wire ack64, req64;

// Unused Development Board Signals
wire lads, last;
wire ldmack0, ldmack1, ldmareq0, ldmareq1;
wire leot0, leot1, linti, lock, lready, lreset, lwr;
wire [3:0] lbe;

// Simulation Control and Status Variables
event SIMEND;
integer transfers, retrys, disconnects, aborts;
reg Master_Abort_Detected, SERR_Detected, InCycle, pass, Disconnect_Detected;
reg PERR_Detected;
reg [128:1] info;
reg [31:0] ReadData, CheckEnables, PerfCount;
reg [31:0] CurRxAddr, CurTxAddr;
reg [31:0] CurRxData, CurTxData;
reg [15:0] CurRxSize, CurTxSize;
reg [31:0] DMACtrlReg;
reg [31:0] DMARxTxCntReg;
integer RxDataCnt, TxDataCnt, LastDMASize, err_cnt;
real PCIBandwidth;
reg DMAWriteEnabled, DMAReadEnabled;
reg InhProtoErr;
reg MstPark, FullSpeed, ParityTest;
reg DummyMstDriving;
integer i,j, index;
reg [1:0] random2;
reg [2:0] random3;
reg [4:0] HalfCycleLocal, HalfCyclePCI;
reg [2:0] local_clock_control;
reg oe_reg;

// CardBus IP signals
reg pad_BAM;
reg [2:1] pad_bvd;
reg pad_clk_resume;
reg pad_CBLOCK_n;
reg pad_PWM, pad_ready, pad_wp;
reg pad_gwake, pad_intr;
reg [31:0] pad_CIS_data;

wire pad_CAUDIO;
//wire pad_CCLKRUN_n;
wire pad_CINT_n;
wire pad_clk_stopped, pad_CSTSCHG;
wire pad_locked, pad_owner_access;
wire [9:2] pad_CIS_ADR;

// Proto Checker Error Codes
parameter 
	ERRIDLE = 8,
	ERRFRAME = 9,
	ERRIRDY = 10,
	ERRTRDY = 11,
	ERRDEVSEL = 12,
	ERRSTOP = 13;


cardbus_5632 m ( .AD(AD[31:0]), .CBEN(CBEN[3:0]), .CLK(CLK), 
	.DEVSELN(DEVSELN), .or_n(or_n), .ir_n(ir_n), .FRAMEN(FRAMEN),.GNTN(GNTN), 
	.IDSEL(IDSEL), .INTAN(INTAN), .IRDYN(IRDYN), .lad(lad),
	.lclk(lclk), .ld(ld), .led(led), .mrs(mrs), .oe(oe), .pae_n(pae_n), 
	.paf_n(paf_n), .PAR(PAR), .PERRN(PERRN), .ren(ren), .REQN(REQN), 
	.RSTN(RSTN), .SERRN(SERRN), .STOPN(STOPN), 
	.TRDYN(TRDYN), .wen(wen),
	// added CardBus IP signals
	.pad_CIS_data(pad_CIS_data),
	.pad_BAM(pad_BAM), .pad_bvd(pad_bvd),
	.pad_CBLOCK_n(pad_CBLOCK_n), .pad_clk_resume(pad_clk_resume), 
	.pad_gwake(pad_gwake), .pad_intr(pad_intr),
	.pad_PWM(pad_PWM), .pad_ready(pad_ready), .pad_wp(pad_wp), 
    .pad_CAUDIO(pad_CAUDIO), .pad_CINT_n(pad_CINT_n),
    .pad_clk_stopped(pad_clk_stopped), .pad_CSTSCHG(pad_CSTSCHG), 
    .pad_locked(pad_locked),
    .pad_owner_access(pad_owner_access), .pad_CCLKRUN_n(pad_CCLKRUN_n),
	.pad_CIS_ADR(pad_CIS_ADR)
	);

tf_pci_master master_2 (
    .reset_l(RSTN),
    .pci_clk(CLK),
    .pci_ad(AD),
    .pci_cbe(CBEN),
    .par(PAR),
    .par_64(par64),
    .frame_l(FRAMEN),
    .irdy_l(IRDYN),
    .trdy_l(TRDYN),
    .stop_l(STOPN),
    .devsel_l(DEVSELN),
    .idsel(IDSEL),
    .req64_l(req64_l),
    .ack64_l(ack64_l),
    .req_l(master_2_req_l),
    .gnt_l(master_2_gnt_l)
    );

defparam master_2.RW_BUFF_SIZE_ADDR_BITS = 8;     // 256 DWORD MEMORY CAPACITY

pci_tar target_1 (
	.clk(CLK),
	.pci_ad(AD),
	.c_be_n(CBEN), 
	.idsel(AD[30]),
	.par(PAR),
    .par64(par64),
	.frame_n(FRAMEN), 
	.irdy_n(IRDYN),  
	.trdy_n(TRDYN),   
	.devsel_n(DEVSELN), 
    .req64_n(req64_l),
    .ack64_n(ack64_l),
	.rst_n(RSTN),  
	.stop_n(STOPN), 
    .perr_n(PERRN)
        );

//Size of memory, in bytes 
defparam target_1.MEM_SIZE = 64'h0000_0000_0001_0000;   
defparam target_1.IO_SIZE = 32'h0000_0100;

// *****************************************************************************
// *****************************************************************************
// COMMAND MONITOR
// *****************************************************************************
// *****************************************************************************

cmd_monitor cmd_mon_1 (
    .ad(AD),
    .cben(CBEN),
    .clk(CLK),
	.devseln(DEVSELN),
	.framen(FRAMEN),
	.idsel(IDSEL),
	.irdyn(IRDYN),
	.par(PAR),
	.perrn(PERRN),
	.rstn(RSTN),
	.serrn(SERRN),
	.stopn(STOPN),
	.trdyn(TRDYN),
	.test_type(test_type),
	.cmd_mon(cmd_mon));
   

// INITIALIZE TARGET CONTROLS //
// (Note: These are all initialized to default values in the module itself, but are set here for clarity)

initial begin
    @(posedge CLK);
    target_1.BASE_ADDRESS <= 64'h0000_0000_1111_0000;  //Base address 
    target_1.BASE_ADDRESS_IO <= 32'h0111_0000;  //I/O Base address 
    target_1.BUS_SIZE <= 32;            //32 or 64 bit bus size
    target_1.DEVICE_SPEED <= 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
    target_1.STOP_COUNT <= 4;           //Assert stop after this many data phases
    target_1.STOP_ENABLE <= 0;          //Enable/Disable stop assertion
    target_1.WAITSTATES_ENABLE <= 0;    //Enable insertion of wait states
    target_1.VARIABLE_WAITS <= 1;       //Enable variable wait lengths (1 or 0)
    target_1.MAX_WAITS <= 2;            //Max # of wait states inserted in variable waits mode
    target_1.MIN_WAITS <= 0;            //Min # of wait states inserted in variable waits mode
    target_1.INITIAL_WAITS <= 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS <= 0;     //# of waits to insert before subsequent trdy's
    target_1.STOP_WAITS <= 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)
    target_1.ENABLE_RETRY_COUNT <= 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
    target_1.RETRY_COUNT <= 4;          //# of retries to force before disabling stop assertion
    target_1.WRONG_PAR <= 0;             //# generate bad parity for lower 32 bits
    target_1.WRONG_PAR64 <= 0;           //# generate bad parity for upper 32 bits
    target_1.PERR_ASSERT <= 0;           //# assert perr even if driven parity matches data
    target_1.TARGET_ABORT <= 0;          //# perform a target abort on all transactions
	target_1.IA_ENABLE <= 1'b1;
	target_1.INTERRUPT_VECTOR <= 32'h78787878;
	end

pci_arbiter arbiter_instance (
	.pci_clk(CLK),
	.request_n({ REQN, master_2_req_l }),
	.grant_n({ GNTN, master_2_gnt_l }),
	.busy((~IRDYN) | (~FRAMEN)),
	.reset_n(RSTN)
	);

defparam arbiter_instance.PCI_MASTER_DEVICES = 2;

initial begin
    @(posedge CLK);
    arbiter_instance.ARBITRATION_STYLE <= 2'b10;  
	//00 = Give grant until it is no longer requested, then go to next device in round robin fashion
	//01 = Give grant until device does first access, then remove and give to next device in round robin fashion
	//10 = Give grant for a fixed timeslice, then give to next in round robin fashion (classic round robin)
	//11 = Unused
    arbiter_instance.TIMESLICE_LENGTH <= 5;  
	end


// CIS ROM
//always @(posedge CLK or negedge RSTN) begin : CIS_ROM
always @(pad_CIS_ADR) begin : CIS_ROM
	if (pad_CIS_ADR[9:8] == 2'b00) begin
		case (pad_CIS_ADR[3:2])
			2'b00:		pad_CIS_data <= 32'h04030201; //0x0
			2'b01:		pad_CIS_data <= 32'h08070605; //0x4
			2'b10:		pad_CIS_data <= 32'h0C0B0A09; //0x8
			2'b11:  	pad_CIS_data <= 32'h100F0E0D; //0xC
			default:	pad_CIS_data <= 32'h00000000; 
		endcase
	end
	else
		pad_CIS_data <= 32'h00000000;		
end
// IDT FIFO

assign #OutDlyLocal lad = oe ? 32'hzzzzzzzz : RXDATA;

always @(posedge lclk or negedge mrs or negedge prs)
	if (~mrs || ~prs) begin
		fcounter <= 0;
		frpointer <= 0;
		fwpointer <= 0;
		ppointer <= 0;
		partialreg[0] <= PARTIAL_FLAG_DEFAULT;
		partialreg[1] <= (FIFO_SIZE - 1) - PARTIAL_FLAG_DEFAULT;
		end
	else begin
		if (~ren) begin
			if (~or_n) begin
				frpointer <= (frpointer == (FIFO_SIZE - 1)) ? 0 : frpointer + 1;
				fcounter <= fcounter - 1;
				end
			end
		if (~wen && ~ld) begin
			partialreg[ppointer] <= lad[31:16];
			ppointer <= ppointer + 1;
			end
		if (~wen && ld) begin
			// fifo[fwpointer] = lad;
			if (~ir_n) begin
				fifo[fwpointer] <= lad;
				fwpointer <= (fwpointer == (FIFO_SIZE - 1)) ? 0 : fwpointer + 1;
				fcounter <= fcounter + 1;
				end
			end
		end

assign RXDATA = fifo[frpointer];

always @(fcounter or partialreg[0] or partialreg[1]) begin
		if (fcounter == 0) or_n <= #OutDlyLocal 1;
			      else or_n <= #OutDlyLocal 0;
		if (fcounter == FIFO_SIZE-1) ir_n <= #OutDlyLocal 1;
			                else ir_n <= #OutDlyLocal 0;
		if (fcounter > ((FIFO_SIZE/2)-1)) hf_n <= #OutDlyLocal 0;
			                     else hf_n <= #OutDlyLocal 1;
		if (fcounter <= partialreg[0])  pae_n <= #OutDlyLocal 0;
			                   else pae_n <= #OutDlyLocal 1;
		if (fcounter >= (FIFO_SIZE - partialreg[1])) 
						paf_n <= #OutDlyLocal 0;
			                   else paf_n <= #OutDlyLocal 1;
		end

// Clocks

initial begin
	HalfCycleLocal = 10;
	HalfCyclePCI = 15;
	end

initial begin : Local_Clock
	lclk = 0;
	#30;
	lclk = 1;
	forever begin
		//#HalfCycleLocal;
                #HalfCyclePCI;
		lclk = ~lclk;
		end
	end

initial begin : PCI_Clock 
	CLK = 0;
	#30;
	CLK = 1;
	forever begin
		#HalfCyclePCI;
		CLK = ~CLK;
		end
	end

always @(s0 or s1) begin
	case ({s1,s0})
		2'b00 : HalfCycleLocal = 0;	 // 14.318 MHz Base Clock
		2'b0z : HalfCycleLocal = 17; // 28.64 MHz
		2'b01 : HalfCycleLocal = 12; // 42.96 MHz
		2'bz0 : HalfCycleLocal = 9; // 57.27 MHz
		2'bzz : HalfCycleLocal = 7; // 71.59 MHz
		2'bz1 : HalfCycleLocal = 6; // 85.91 MHz
		2'b10 : HalfCycleLocal = 5; // 100.2 MHz
		2'b1z : HalfCycleLocal = 4; // 114.6 MHz
		2'b11 : HalfCycleLocal = 12; // 229.1 MHz
		default: HalfCycleLocal = 7; // Standard Value because s1, s0 pins removed
					     // due to not enough I/O pins.
		endcase
	end