cardbus_wrapper_test.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 105 行

/*-----------------------------------------------------------------------
--	  File : cardbus_wrapper_test.tf
--   
--    DESCRIPTION: 
--			This file provides all CardBus signals (in addition to PCI signals),
--			as well as registers and logic to support those new signals.
--
--    HIERARCHY:  
--			 This file is used in the top-level design, to "wrap-around" the PCI core
--
--    AUTHOR: David Shih
--
--    HISTORY: 
--    Date	        Author					Version
--    10/26/03		David Shih				1.0
--		- Initial release
--		
-- Copyright (C) 2003, Licensed Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
--
-- IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
-- This design is provided without warranty of any kind.
-- QuickLogic Corporation does not warrant, guarantee or make any representations
-- regarding the use, or the results of the use, of this design. QuickLogic
-- disclaims all implied warranties, including but not limited to implied
-- warranties of merchantability and fitness for a particular purpose. In addition
-- and without limiting the generality of the foregoing, QuickLogic does not make
-- any warranty of any kind that any item developed based on this design, or any
-- portion of it, will not infringe any copyright, patent, trade secret or other
-- intellectual property right of any person or entity in any country. It is the
-- responsibility of the user of the design to seek licenses for such intellectual
-- property rights where applicable. QuickLogic shall not be liable for any
-- damages arising out of or in connection with the use of the design including
-- liability for lost profit, business interruption, or any other damages whatsoever.
--
-----------------------------------------------------------------------*/



`timescale 1ns/1ns

module t;

reg CCLK;
reg CRST_n;
reg BAM_in;
reg PWM_in;
reg clk_resume;
reg addr_phase;
reg framen_d1;
reg usr_read;
reg usr_write;
reg [11:0]	user_addr;
reg intr_ps;
reg gwake_ps;
reg [2:1]	bvd_ps;
reg ready_ps;
reg wp_ps;
reg BAR_match;
wire [31:0]	cstschg_regs_bus;
wire CBLOCK_n;
wire CCLKRUN_n;
wire CINT_n;
wire CSTSCHG;
wire CAUDIO_n;
wire clk_stopped;
wire locked;
wire owner_access;

    cardbus_wrapper m (	// outputs	
		.CINT_n(CINT_n),
		.CSTSCHG(CSTSCHG),
		.CAUDIO_n(CAUDIO_n),
		.clk_stopped(clk_stopped),
		.locked(locked),
		.owner_access(owner_access),

		// inouts
		.cstschg_regs_bus(cstschg_regs_bus),		
		.CCLKRUN_n(CCLKRUN_n),
		.CBLOCK_n(CBLOCK_n),
		
		// inputs
		.BAM_in(BAM_in),
		.PWM_in(PWM_in),
		.CCLK(CCLK),
		.CRST_n(CRST_n),
		.clk_resume(clk_resume),
		.addr_phase(addr_phase),
		.framen_d1(framen_d1),
		.usr_read(usr_read),
		.usr_write(usr_write),
		.user_addr(user_addr),
		.intr_ps(intr_ps),		
		.gwake_ps(gwake_ps),
		.bvd_ps(bvd_ps),
		.ready_ps(ready_ps),
		.wp_ps(wp_ps),
		.BAR_match(BAR_match);

    // Enter fixture code here

endmodule // t

	)