ucnt6.v

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· Verilog 代码 · 共 33 行

`timescale 1ns/1ns
`define ucnt6
/************************************************************************
** File : ucnt6.v
** Design Date: June 9, 1998
** Creation Date: Thu Sep 21 17:00:30 2000

** Created By SpDE Version: SpDE 8.2 
** Author: Brian Faith, QuickLogic Corporation,
** Copyright (C) 1998, Customers of QuickLogic may copy and modify this
** file for use in designing QuickLogic devices only.
** Description: This is the counter for generating the read
** and write addresses in the FIFOs.
************************************************************************/
module ucnt6 (enable, clk, q, rst);

// inputs: enable,clk,rst
// outputs: =q[5:0]=

input enable, clk, rst;
output [5:0] q;
reg [5:0] q;

always @(posedge clk or posedge rst) begin
   if (rst)
      q <= #1 0;
   else if (enable)
      q <= #1 q + 1;
   else
      q <= #1 q;
end
endmodule