ct_master.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 949 行 · 第 1/4 页

TF
949 行
字号
1234
	mrl <= 1'b1;
	`include "ct_parity_error.tf"
	mrl <= 1'b0;
$display("Master MRM and MWI, Multi-Cycle Data Parity Error Test, %0d", $time);
	mrm <= 1'b1;
	`include "ct_parity_error.tf"
	mrm <= 1'b0;
	mem <= 1'b0;
$display("Master Configuration Read and Write, Multi-Cycle Data Parity Error Test, %0d", $time);
	cfg <= 1'b1;
	`include "ct_parity_error.tf"
	cfg <= 1'b0;

$display("Resetting QuickPCI Device");
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200010C,64'h00000000,MEM_WRITE,8'hFF,0,0,1,1,1,0); 


target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
target_1.WRONG_PAR = 0;             //# generate bad parity for lower 32 bits
target_1.PERR_ASSERT = 0;           //# assert perr even if driven parity matches data
target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
target_1.XFER_COUNT = 1;           // Number of PCI transfers that must take place between target waits
target_1.VARIABLE_WAITS = 0;       //Enable variable wait lengths (1 or 0)
target_1.TARGET_ABORT = 0;
target_1.TABORT_COUNT = 0;
target_1.TABORT_ENABLE = 0;
target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_ENABLE = 0;          //Enable/Disable stop assertion
target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
target_1.STOP_WAITS = 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)
arbiter_instance.TIMESLICE_LENGTH = 8;

arbiter_instance.ARBITRATION_STYLE <= 2'b10;  
//00 = Give grant until it is no longer requested, then go to next device in round robin fashion
//01 = Give grant until device does first access, then remove and give to next device in round robin fashion
//10 = Give grant for a fixed timeslice, then give to next in round robin fashion (classic round robin)
//11 = Unused
arbiter_instance.TIMESLICE_LENGTH <= 5;

$display("Master Mem Read and Write, Latency Timer Expiration Test, %0d", $time);
	mem <= 1'b1;
	`include "ct_burst_latency_timeout.tf"
$display("Master MRL and MWI, Latency Timer Expiration Test, %0d", $time);
	mrl <= 1'b1;
	`include "ct_burst_latency_timeout.tf"
	mrl <= 1'b0;
$display("Master MRM and MWI, Latency Timer Expiration Test, %0d", $time);
	mrm <= 1'b1;
	`include "ct_burst_latency_timeout.tf"
	mrm <= 1'b0;
	mem <= 1'b0;
$display("Master Configuration Read and Write, Latency Timer Expiration Test, %0d", $time);
	cfg <= 1'b1;
	`include "ct_burst_latency_timeout.tf"
	cfg <= 1'b0;

$display("Resetting QuickPCI Device");
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200010C,64'h00000000,MEM_WRITE,8'hFF,0,0,1,1,1,0); 


$display("Master Bus Park Test, %0d", $time);
	arbiter_instance.ARBITRATION_STYLE = 0;
	arbiter_instance.TIMESLICE_LENGTH = 20;
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h11118000,64'h0,MEM_WRITE,8'hFF,0,0,6,1,1,0); 
	// enable bus master and clear status bits
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// set latency timer to 7 clocks
	repeat (5) @(posedge CLK);
	master_2.target_access(32'hC,64'h00000700,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// Configure and enable a 1 cycle DMA read from the Target
	master_2.data_array[0] = 32'h00060006;
	master_2.data_array[1] = 32'h11118000 >> 2;
	master_2.data_array[2] = 32'h11110000 >> 2;
	master_2.data_array[3] = 32'hCD000000;
	for (i = 0; i < 5; i = i + 1) begin
		master_2.be_array[i] = 4'hF;
		end
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,4,1,1,0);
	//Wait for Master DMA to complete
	repeat (50) @(posedge CLK);
	// Bus should be parked on Master under test...
	// Now release grant and grant to secondary master...
	master_2.target_access(32'h22000100,64'h0,MEM_READ,8'hFF,0,0,4,1,1,0);

$display("Resetting QuickPCI Device");
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200010C,64'h00000000,MEM_WRITE,8'hFF,0,0,1,1,1,0); 


arbiter_instance.ARBITRATION_STYLE = 2'b10;
arbiter_instance.TIMESLICE_LENGTH = 1;
target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
target_1.WRONG_PAR = 0;             //# generate bad parity for lower 32 bits
target_1.PERR_ASSERT = 0;           //# assert perr even if driven parity matches data
target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
target_1.XFER_COUNT = 1;           // Number of PCI transfers that must take place between target waits
target_1.VARIABLE_WAITS = 0;       //Enable variable wait lengths (1 or 0)
target_1.TARGET_ABORT = 0;
target_1.TABORT_COUNT = 0;
target_1.TABORT_ENABLE = 0;
target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_ENABLE = 0;          //Enable/Disable stop assertion
target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
target_1.STOP_WAITS = 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

$display("Master Mem Read and Write Arbitration Test, %0d", $time);
	mem <= 1'b1;
	`include "ct_arbitration.tf"
$display("Master MRL and MWI Arbitration Test, %0d", $time);
	mrl <= 1'b1;
	`include "ct_arbitration.tf"
	mrl <= 1'b0;
$display("Master MRM and MWI Arbitration Test, %0d", $time);
	mrm <= 1'b1;
	`include "ct_arbitration.tf"
	mrm <= 1'b0;
	mem <= 1'b0;
$display("Master I/O Read and Write Arbitration Test, %0d", $time);
	io <= 1'b1;
	`include "ct_arbitration.tf"
	io <= 1'b0;
$display("Master Configuration Read and Write Arbitration Test, %0d", $time);
	cfg <= 1'b1;
	`include "ct_arbitration.tf"
	cfg <= 1'b0;
$display("Master Interrupt Acknowledge Arbitration Test, %0d", $time);
	ia <= 1'b1;
	`include "ct_arbitration.tf"
	ia <= 1'b0;
$display("Master Special cycle Arbitration Test, %0d", $time);
	sc <= 1'b1;
	`include "ct_arbitration.tf"
	sc <= 1'b0;


$display("Target Back to back Transfer Test (Write/Write, Write/Read - same target)");
$display("  (Frame Protocal Errors are expected)");
	arbiter_instance.ARBITRATION_STYLE = 2'b10;
	arbiter_instance.TIMESLICE_LENGTH = 1;
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
    target_1.WRONG_PAR = 0;             //# generate bad parity for lower 32 bits
    target_1.PERR_ASSERT = 0;           //# assert perr even if driven parity matches data
    target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 1;           // Number of PCI transfers that must take place between target waits
	target_1.VARIABLE_WAITS = 0;       //Enable variable wait lengths (1 or 0)
	target_1.TARGET_ABORT = 0;
	target_1.TABORT_COUNT = 0;
	target_1.TABORT_ENABLE = 0;
	target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
    target_1.STOP_ENABLE = 0;          //Enable/Disable stop assertion
    target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
    target_1.STOP_WAITS = 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h11118000,64'h0,MEM_WRITE,8'hFF,0,0,6,1,1,0); 
	// enable bus master and clear status bits
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// set latency timer to 32 clocks
	repeat (5) @(posedge CLK);
	master_2.target_access(32'hC,64'h00002000,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// Prepare a 6 cycle DMA read from the Target
	master_2.data_array[0] = 32'h00060006;
	master_2.data_array[1] = 32'h11118000 >> 2;
	master_2.data_array[2] = 32'h11110000 >> 2;
	for (i = 0; i < 5; i = i + 1) begin
		master_2.be_array[i] = 4'hF;
		end
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,3,0,0,0);
	// back to back transfer, changing size and data locations
	master_2.data_array[0] = 32'hAAAAAAAA;
	master_2.data_array[1] = 32'h11118100 >> 2;
	master_2.data_array[2] = 32'h11110100 >> 2;
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,3,0,0,0);
	//check data with a back to back read!
	master_2.data_array[1] = 32'h11118100;
	master_2.data_array[2] = 32'h11110100;
	master_2.target_access_pf(32'h22000100,32'h0,MEM_READ_MULT,8'hFF,0,0,3,0,0,0, pass, 0);

$display("Target Back to Back Transfer Test (Write/Write, Write/Read - different targets)");
$display("  (Frame Protocal Errors are expected)");
	arbiter_instance.ARBITRATION_STYLE = 2'b10;
	arbiter_instance.TIMESLICE_LENGTH = 1;
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
    target_1.WRONG_PAR = 0;             //# generate bad parity for lower 32 bits
    target_1.PERR_ASSERT = 0;           //# assert perr even if driven parity matches data
    target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 1;           // Number of PCI transfers that must take place between target waits
	target_1.VARIABLE_WAITS = 0;       //Enable variable wait lengths (1 or 0)
	target_1.TARGET_ABORT = 0;
	target_1.TABORT_COUNT = 0;
	target_1.TABORT_ENABLE = 0;
	target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
    target_1.STOP_ENABLE = 0;          //Enable/Disable stop assertion
    target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
    target_1.STOP_WAITS = 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)
	// enable bus master and clear status bits
	master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// set latency timer to 32 clocks
	master_2.target_access(32'hC,64'h00002000,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// Write a 0 to the first memory location in the secondary target
	master_2.target_access(32'h11118000,64'h0,MEM_WRITE,8'hFF,0,0,1,1,1,0); 
	// Write 3 data elemts to the DMA registers in the primary Target (back to back)
	master_2.data_array[0] = 32'hBBBBBBBB;
	master_2.data_array[1] = 32'h01012020 >> 2;
	master_2.data_array[2] = 32'h2020a0a0 >> 2;
	for (i = 0; i < 5; i = i + 1) begin
		master_2.be_array[i] = 4'hF;
		end
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,3,0,0,0);
	// back to back transfer, writing a 0 again to the secondary target
	master_2.target_access(32'h11118000,64'h0,MEM_WRITE,8'hFF,0,0,1,1,1,0); 
	//read and check data with a back to back read!
	master_2.data_array[0] = 32'hBBBBBBBB;
	master_2.data_array[1] = 32'h01012020;
	master_2.data_array[2] = 32'h2020a0a0;
	master_2.target_access_pf(32'h22000100,32'h0,MEM_READ_MULT,8'hFF,0,0,3,0,0,0, pass, 0);

repeat (5) @(posedge CLK);
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ct_master.tf - 源码说明

本页面展示了「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」中的 ct_master.tf 源码文件，采用 TF 编程语言编写，共 949 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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