ct_master.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 949 行 · 第 1/4 页

TF
949 行
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	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"

mrl <= 1'b1;
$display("Master MRL and MWI to a Fast Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Medium Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Slow Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Subtractive Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
mrl <= 1'b0;

mrm <= 1'b1;
$display("Master MRM and MWI to a Fast Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Medium Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Slow Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Subtractive Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
mrm <= 1'b0;
mem <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Medium Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Slow Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
cfg <= 1'b0;

multi_retry <= 1'b0;


multi_disconnect <= 1'b1;

target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
target_1.STOP_WAITS = 0;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

mem <= 1'b1;
$display("Master Mem Read and Write to a Fast Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Medium Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Slow Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"

mrl <= 1'b1;
$display("Master MRL and MWI to a Fast Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Medium Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Slow Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Subtractive Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
mrl <= 1'b0;

mrm <= 1'b1;
$display("Master MRM and MWI to a Fast Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Medium Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Slow Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Subtractive Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
mrm <= 1'b0;
mem <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Medium Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Slow Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Speed Target w/ Multi-Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
cfg <= 1'b0;

multi_disconnect <= 1'b0;


target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
target_1.XFER_COUNT = 1;           // Number of PCI transfers that must take place between target waits
target_1.VARIABLE_WAITS = 0;       //Enable variable wait lengths (1 or 0)
target_1.TARGET_ABORT = 0;
target_1.TABORT_COUNT = 0;
target_1.TABORT_ENABLE = 0;
target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_ENABLE = 0;          //Enable/Disable stop assertion
target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
target_1.STOP_WAITS = 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

$display("Master Single Wait State, First Data Cycle Test, %0d", $time);
	target_1.INITIAL_WAITS = 2;        //# of waits to insert before first trdy
	target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
	`include "ct_burst_r_w_ws.tf"
$display("Master Single Wait State, Second Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 1;     //# of waits to insert before subsequent trdy's
	`include "ct_burst_r_w_ws.tf"
$display("Master Two Wait States, 2nd and 3rd Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 2;           // Number of PCI transfers that must take place between target waits
	`include "ct_burst_r_w_ws.tf"
$display("Master Two Wait States, 3rd and 4th Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 2;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 2;           // Number of PCI transfers that must take place between target waits
	`include "ct_burst_r_w_ws.tf"

mrl <= 1'b1;
$display("Master MRL & MWI Single Wait State, First Data Cycle Test, %0d", $time);
	target_1.INITIAL_WAITS = 2;        //# of waits to insert before first trdy
	target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
	`include "ct_burst_r_w_ws.tf"
$display("Master MRL & MWI Single Wait State, Second Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 1;     //# of waits to insert before subsequent trdy's
	`include "ct_burst_r_w_ws.tf"
$display("Master MRL & MWI Two Wait States, 2nd and 3rd Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 2;           // Number of PCI transfers that must take place between target waits
	`include "ct_burst_r_w_ws.tf"
$display("Master MRL & MWI Two Wait States, 3rd and 4th Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 2;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 2;           // Number of PCI transfers that must take place between target waits
	`include "ct_burst_r_w_ws.tf"
mrl <= 1'b0;

mrm <= 1'b1;
$display("Master MRM & MWI Single Wait State, First Data Cycle Test, %0d", $time);
	target_1.INITIAL_WAITS = 2;        //# of waits to insert before first trdy
	target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
	`include "ct_burst_r_w_ws.tf"
$display("Master MRM & MWI Single Wait State, Second Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 1;     //# of waits to insert before subsequent trdy's
	`include "ct_burst_r_w_ws.tf"
$display("Master MRM & MWI Two Wait States, 2nd and 3rd Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 2;           // Number of PCI transfers that must take place between target waits
	`include "ct_burst_r_w_ws.tf"
$display("Master MRM & MWI Two Wait States, 3rd and 4th Data Cycle Test, %0d", $time);
    target_1.INITIAL_WAITS = 2;        //# of waits to insert before first trdy
    target_1.SUBSEQUENT_WAITS = 2;     //# of waits to insert before subsequent trdy's
	target_1.XFER_COUNT = 2;           // Number of PCI transfers that must take place between target waits
	`include "ct_burst_r_w_ws.tf"
mrm <= 1'b0;


single_parity_error <= 1'b1;

target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
target_1.WRONG_PAR = 0;             //# generate bad parity for lower 32 bits
target_1.PERR_ASSERT = 0;           //# assert perr even if driven parity matches data
target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS = 0;     //# of waits to insert before subsequent trdy's
target_1.XFER_COUNT = 1;           // Number of PCI transfers that must take place between target waits
target_1.VARIABLE_WAITS = 0;       //Enable variable wait lengths (1 or 0)
target_1.TARGET_ABORT = 0;
target_1.TABORT_COUNT = 0;
target_1.TABORT_ENABLE = 0;
target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_ENABLE = 0;          //Enable/Disable stop assertion
target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
target_1.STOP_WAITS = 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

$display("Master Mem Read and Write, Single Cycle Data Parity Error Test, %0d", $time);
	mem <= 1'b1;
	`include "ct_parity_error.tf"
	mem <= 1'b0;

$display("Master I/O Read and Write, Single Cycle Data Parity Error Test, %0d", $time);
	io <= 1'b1;
	`include "ct_parity_error.tf"
	io <= 1'b0;

$display("Master Configuration Read and Write, Single Cycle Data Parity Error Test, %0d", $time);
	cfg <= 1'b1;
	`include "ct_parity_error.tf"
	cfg <= 1'b0;

single_parity_error <= 1'b0;


$display("Master Read and Write, Multi-Cycle Data Parity Error Test, %0d", $time);
	mem <= 1'b1;
	`include "ct_parity_error.tf"
$display("Master MRL and MWI, Multi-Cycle Data Parity Error Test, %0d", $time);
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ct_master.tf - 源码说明

本页面展示了「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」中的 ct_master.tf 源码文件，采用 TF 编程语言编写，共 949 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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