ct_master.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 949 行 · 第 1/4 页

TF
949 行
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	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Subtractive Decode Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
ia <= 1'b0;

single_target_abort <= 1'b0;

$display("\nResetting QuickPCI Device\n");
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h00000000,MEM_WRITE,8'hFF,0,0,1,1,1,0); 


single_retry <= 1'b1;

target_1.WAITSTATES_ENABLE <= 1;    //Enable insertion of wait states
target_1.VARIABLE_WAITS <= 0;       //Enable variable wait lengths (1 or 0)
target_1.INITIAL_WAITS <= 2;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS <= 0;     //# of waits to insert before subsequent trdy's
target_1.ENABLE_RETRY_COUNT = 1;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_COUNT = 0;           //Assert stop after this many data phases
target_1.STOP_WAITS = 0;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

mem <= 1'b1;
$display("Master Mem Read and Write to a Fast Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Medium Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Slow Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Decode Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
mem <= 1'b0;

io <= 1'b1;
$display("Master I/O Read and Write to a Fast Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Medium Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Slow Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Subtractive Decode Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
io <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Medium Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Slow Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Decode Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
cfg <= 1'b0;

ia <= 1'b1;
$display("Master Interrupt Acknowledge to a Fast Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Medium Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Slow Speed Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Subtractive Decode Target w/ 1 Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
ia <= 1'b0;

single_retry <= 1'b0;


single_disconnect <= 1'b1;

target_1.ENABLE_RETRY_COUNT = 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_COUNT = 1;           //Assert stop after this many data phases
target_1.STOP_WAITS = 0;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

mem <= 1'b1;
$display("\nMaster Mem Read and Write to a Fast Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Medium Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Slow Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Decode Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
mem <= 1'b0;

io <= 1'b1;
$display("Master I/O Read and Write to a Fast Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Medium Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Slow Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Subtractive Decode Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
io <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Medium Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Slow Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Decode Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
cfg <= 1'b0;

ia <= 1'b1;
$display("Master Interrupt Acknowledge to a Fast Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Medium Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Slow Speed Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Subtractive Decode Target w/ 1 Cycle Disconnect Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
ia <= 1'b0;

single_disconnect <= 1'b0;


multi_target_abort <= 1'b1;

mem <= 1'b1;
$display("Master Mem Read and Write to a Fast Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Medium Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Slow Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"

mrl <= 1'b1;
$display("Master MRL and MWI to a Fast Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Medium Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Slow Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRL and MWI to a Subtractive Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
mrl <= 1'b0;

mrm <= 1'b1;
$display("Master MRM and MWI to a Fast Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Medium Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Slow Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master MRM and MWI to a Subtractive Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
mrm <= 1'b0;
mem <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Medium Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Slow Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Target w/ Multi-Cycle Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
cfg <= 1'b0;

multi_target_abort <= 1'b0;


multi_retry <= 1'b1;

target_1.WAITSTATES_ENABLE <= 1;    //Enable insertion of wait states
target_1.VARIABLE_WAITS <= 0;       //Enable variable wait lengths (1 or 0)
target_1.INITIAL_WAITS <= 2;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS <= 0;     //# of waits to insert before subsequent trdy's
target_1.ENABLE_RETRY_COUNT = 1;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.STOP_COUNT = 0;           //Assert stop after this many data phases
target_1.STOP_WAITS = 0;           //# waits to pause before asserting stop(after STOP_COUNT data phases)

mem <= 1'b1;
$display("Master Mem Read and Write to a Fast Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Medium Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_burst_r_w.tf"
$display("Master Mem Read and Write to a Slow Speed Target w/ Multi-Cycle Retry Test, %0d", $time);
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ct_master.tf - 源码说明

本页面展示了「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」中的 ct_master.tf 源码文件，采用 TF 编程语言编写，共 949 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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