ct_master.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 949 行 · 第 1/4 页

TF
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//------------------------------------------------------------------------------
//
// File : ct_master.tf
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	PCI master tests of the PCI compliance test suite.
//	 
// Hierarchy:
//	This file is to be included by pci5(3/4)32_280.tf.
//
// History:	
//	Date	        Author					Version
//	10/14/00		Richard Yuan			1.0
//		- Initial release. Modified from 5032 version.
//	06/26/01		Richard Yuan			1.1
//		- Header reorganized to conform to coding standard.
//
//------------------------------------------------------------------------------


target_1.STOP_COUNT <= 4;           //Assert stop after this many data phases
target_1.STOP_ENABLE <= 0;          //Enable/Disable stop assertion
target_1.WAITSTATES_ENABLE <= 0;    //Enable insertion of wait states
target_1.VARIABLE_WAITS <= 1;       //Enable variable wait lengths (1 or 0)
target_1.MAX_WAITS <= 2;            //Max # of wait states inserted in variable waits mode
target_1.MIN_WAITS <= 0;            //Min # of wait states inserted in variable waits mode
target_1.INITIAL_WAITS <= 1;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS <= 0;     //# of waits to insert before subsequent trdy's
target_1.STOP_WAITS <= 1;           //# waits to pause before asserting stop(after STOP_COUNT data phases)
target_1.ENABLE_RETRY_COUNT <= 0;   //# enable stop_enable shut-off after RETRY_COUNT stop assertions
target_1.RETRY_COUNT <= 4;          //# of retries to force before disabling stop assertion
target_1.WRONG_PAR <= 0;             //# generate bad parity for lower 32 bits
target_1.WRONG_PAR64 <= 0;           //# generate bad parity for upper 32 bits
target_1.PERR_ASSERT <= 0;           //# assert perr even if driven parity matches data
target_1.TARGET_ABORT <= 0;          //# perform a target abort on all transactions
target_1.IA_ENABLE <= 1'b1;

$display("Resetting Local Clock Frequency to ~70 MHz for DMA Testing");
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h22000114,32'h0,MEM_WRITE,8'hFF,0,0,1,1,1,0); 


mem <= 1'b1;
$display("Master Mem Read and Write to a Fast Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Medium Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Slow Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Decode Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Slower Than Subtractive Decode Target Test, %0d", $time);
	slower_than_subtractive <= 1'b1;
	`include "ct_single_r_w.tf"
	slower_than_subtractive <= 1'b0;
mem <= 1'b0;

io <= 1'b1;
$display("Master I/O Read and Write to a Fast Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Medium Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Slow Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Subtractive Decode Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Slower Than Subtractive Decode Target Test, %0d", $time);
	slower_than_subtractive <= 1'b1;
	`include "ct_single_r_w.tf"
	slower_than_subtractive <= 1'b0;
io <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Medium Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Slow Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Decode Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Slower Than Subtractive Decode Target Test, %0d", $time);
	slower_than_subtractive <= 1'b1;
	`include "ct_single_r_w.tf"
	slower_than_subtractive <= 1'b0;
cfg <= 1'b0;

ia <= 1'b1;
$display("Master Interrupt Acknowledge to a Fast Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Medium Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Slow Speed Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Subtractive Decode Target Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Slower Than Subtractive Decode Target Test, %0d", $time);
	slower_than_subtractive <= 1'b1;
	target_1.IA_ENABLE <= 1'b0;
	`include "ct_single_r_w.tf"
	slower_than_subtractive <= 1'b0;
	target_1.IA_ENABLE <= 1'b1;
ia <= 1'b0;

$display("Master Special Cycle Test, %0d", $time);
	// enable bus master and clear status bits
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// write special cycle message to location 11C in QL part
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h2200011C,64'hABCDEFAB,MEM_WRITE,8'hFF,0,0,1,1,1,0); 
	// Configure and enable a 1 cycle DMA write from the Target
	master_2.data_array[0] = 32'h00010001;
	master_2.data_array[1] = 32'h00000000 >> 2;
	master_2.data_array[2] = 32'h00000000 >> 2;
	master_2.data_array[3] = {16'hC000,8'b00_0_011_01,8'b01_000000};

	for (i = 0; i < 5; i = i + 1) begin
		master_2.be_array[i] = 4'hF;
		end
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,4,1,1,0); 
	//Wait for Master DMA to complete
	for (i = 0; i < 20; i = i + 1) begin
		repeat (20) @(posedge CLK);
		master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
		if (master_2.data_read[9:8] == 2'b00) begin
			$display("\tMaster DMA Completed Successfully at %0d", $time);
			i = 300;
			end
		if (master_2.data_read[9:8] == 2'b10) begin
			$display("\tMaster DMA did not complete at %0d", $time);
			i = 300;
			end
		end
	if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout) at %0d", $time);
	repeat (5) @(posedge CLK);

	// read test pattern from location 11C in QL part
	$display("\tComparing Data");
	repeat (5) @(posedge CLK);
	master_2.target_access_pf(32'h11110000,32'hABCDEFAB,MEM_READ,8'hFF,0,0,1,1,1,0, pass, 0); 
	// clear FIFO
	repeat (5) @(posedge CLK);
	master_2.target_access_pf(32'h11110000,32'h80018001,MEM_WRITE,8'hFF,0,0,1,1,1,0, pass, 0); 

	// Check Master Abort status bit
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0146,CONFIG_READ,8'hFF,0,0,1,1,1,0);
	if (master_2.data_read[29] == 1) begin
		$display("\tMaster Abort Status Bit Set ... Failed");
		repeat (5) @(posedge CLK);
		master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
		end
	else $display("\tMaster Abort Status Bit Not Set ... Passed"); 


single_target_abort <= 1'b1;

mem <= 1'b1;
$display("\nMaster Mem Read and Write to a Fast Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Medium Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Slow Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Mem Read and Write to a Subtractive Decode Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
mem <= 1'b0;

io <= 1'b1;
$display("Master I/O Read and Write to a Fast Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	single_target_abort <= 1'b1;
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Medium Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Slow Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master I/O Read and Write to a Subtractive Decode Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
io <= 1'b0;

cfg <= 1'b1;
$display("Master Configuration Read and Write to a Fast Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	single_target_abort <= 1'b1;
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Medium Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Slow Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Configuration Read and Write to a Subtractive Decode Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b11;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
cfg <= 1'b0;

ia <= 1'b1;
$display("Master Interrupt Acknowledge to a Fast Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b00;     //0=fast, 1=medium, 2=slow, 3=bridge
	single_target_abort <= 1'b1;
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Medium Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b01;     //0=fast, 1=medium, 2=slow, 3=bridge
	`include "ct_single_r_w.tf"
$display("Master Interrupt Acknowledge to a Slow Target w/ Target Abort Test, %0d", $time);
	target_1.DEVICE_SPEED = 2'b10;     //0=fast, 1=medium, 2=slow, 3=bridge
1234

ct_master.tf - 源码说明

本页面展示了「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」中的 ct_master.tf 源码文件，采用 TF 编程语言编写，共 949 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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