rgec5_2.v

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· Verilog 代码 · 共 40 行

//------------------------------------------------------------------------------
//
// File : rgec5_2.v
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	5-bit register with a reset value of 3 (grey code of 2).
//
// Hierarchy:
//	This file represents the rgec5_2 block in f32a32.sch.
//
// History:	
//	Date	        Author					Version
//  06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


module rgec5_2 ( CLK, CLR, EN, D, Q );
input CLK, CLR, EN;
input  [4:0] D;
output [4:0] Q;
reg    [4:0] Q;

always @(posedge CLR or posedge CLK)
begin
    if (CLR)    // reset grey 2 = bin 3
        Q <= 3;
    else if (EN)   // load
        Q <= D;
end

endmodule