cis_decode.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

/*-----------------------------------------------------------------------
--	  File : CIS_decode.v
--   
--    DESCRIPTION: 
--			This file decodes the User address and flags the user design if
--			CIS data is accessed.
--
--    HIERARCHY:  
--			 This file is used in the top-level design as part of user design
--
--    AUTHOR: Claire Pian Tu
--
--    HISTORY: 
--    Date	        Author					Version
--    04/07/04		Claire Pian Tu			1.0
--		- Initial release
--
--		
-- Copyright (C) 2003, Licensed Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
--
-- IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
-- This design is provided without warranty of any kind.
-- QuickLogic Corporation does not warrant, guarantee or make any representations
-- regarding the use, or the results of the use, of this design. QuickLogic
-- disclaims all implied warranties, including but not limited to implied
-- warranties of merchantability and fitness for a particular purpose. In addition
-- and without limiting the generality of the foregoing, QuickLogic does not make
-- any warranty of any kind that any item developed based on this design, or any
-- portion of it, will not infringe any copyright, patent, trade secret or other
-- intellectual property right of any person or entity in any country. It is the
-- responsibility of the user of the design to seek licenses for such intellectual
-- property rights where applicable. QuickLogic shall not be liable for any
-- damages arising out of or in connection with the use of the design including
-- liability for lost profit, business interruption, or any other damages whatsoever.
--
-----------------------------------------------------------------------*/

module cis_decode
	(	// outputs	
		CIS_Hit,
		clk,
		reset,
		addr_phase,
		last_cycle,
		user_addr,
		BAR_match
	 );

// input output ports
input	clk;			// CardBus clock
input	reset;			// CardBus reset
input	addr_phase;		// CardBus address phase; connect to core's Usr_Addr_Valid
input 	last_cycle;		// CardBus user last cycle flag; connect to core's Usr_Last_Cycle_D1
input	[9:4]	user_addr;	// pci addr, width depends on the user
input			BAR_match;			// CS for BAR in which FcnEventReg are located
output	CIS_Hit;   		// Flag to indicate access to CIS data
 // CIS flag
reg			CIS_Hit;

//CT added this portion for flagging CIS data read
always @(posedge clk or posedge reset) begin
	if (reset)
		CIS_Hit <= 1'b0;
	else begin
		if (BAR_match == 1'b1 && addr_phase == 1'b1 && user_addr[9:4] == 6'h00) 
			CIS_Hit <= 1'b1;
		else if (last_cycle == 1'b1)
			CIS_Hit <= 1'b0;
	end
end

endmodule