r128a8.v

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· Verilog 代码 · 共 36 行

`ifdef r128a8
`else
`define r128a8
`include "d:/pasic/spde/data/ram128x9.v"
/************************************************************************
** File : r128a8.v
** Design Date: June 9, 1998
** Creation Date: Fri Sep 22 13:40:44 2000

** Created By SpDE Version: SpDE 8.2 
** Author: Robert Maul, QuickLogic Corporation,
** Copyright (C) 1998, Customers of QuickLogic may copy and modify this
** file for use in designing QuickLogic devices only.
** Description : This file is autogenerated RTL code that describes the
** connectivity of cascaded RAM blocks (RAM banks) using QuickLogic's
** RAM block resources.
************************************************************************/

module r128a8(wa,ra,wd,rd,we,wclk);

// inputs: =wa[6:0]=,=ra[6:0]=,=wd[7:0]=,we,wclk
// outputs: =rd[7:0]=

input we;
input wclk;
input [6:0] wa;
input [6:0] ra;
input [7:0] wd;
output [7:0] rd;
supply0 GND;
supply1 VCC;
RAM128X9 r128a8I1 (.WA(wa),.RA(ra),.WD({wd[7],wd[6],wd[5],wd[4],wd[3],wd[2],wd[1],wd[0], GND}),.RD({rd[7],rd[6],rd[5],rd[4],rd[3],rd[2],rd[1],rd[0], dummy0}),
  .WE(we),.RE(GND),.WCLK(wclk),.RCLK(GND),.ASYNCRD(VCC));
endmodule
`endif