cardbus_5632.prj

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

#-- Synplicity, Inc.
#-- Version 7.2.1      
#-- Project file D:\project\CardBus\Source\verilog\cardbus_5632.prj
#-- Written on Wed Apr 07 21:51:57 2004


#add_file options
add_file -verilog "cardbus_5632.v"
add_file -_pasic "CARDBUS_5632.sc"


#implementation: "verilog"
impl -add verilog

#device options
set_option -technology ECLIPSE
set_option -part QL5632-33
set_option -package pt280
set_option -speed_grade -7

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -fanout_limit 16
set_option -disable_io_insertion 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./CARDBUS_5632.qdf"

#implementation attributes
set_option -compiler_compatible ""
impl -active "verilog"