📄 pci5632_280.v
字号:
/* Verilog Model Created from SCS Schematic pci5632_280.sch
Aug 05, 2002 13:06 */
/* Automatically generated by hvveri version 9.3 Release Build1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR 2
`define INCELL 3
`define CLOCK 4
`define HSCK 5
`define CLOCKB 6
`define ESPXCLKIN 7
`define HSCKMUX 8
`define IOCONTROL 9
`include "cfgtaddr_5632_280.v"
`include "c:/pasic/spde/data/ql5632-33/PCI32_25UM/pci32_25um.v"
`include "f64x4.v"
`include "dmaregrd.v"
`include "fifocont.v"
`include "initflgs.v"
`include "dmacntrl.v"
`include "r128x32_25um.v"
`include "gcnte5_0.v"
`include "rgec5_1r.v"
`include "rgec5_2.v"
`include "gcnte5_2.v"
`include "gcnte5_3.v"
module pci5632_280( CLK , GNTN, IDSEL, ir_n, lclk, or_n, pae_n, paf_n, RSTN,
INTAN, ld, led, mrs, oe, ren, REQN, SERRN, wen, AD, CBEN,
DEVSELN, FRAMEN, IRDYN, lad, PAR, PERRN, STOPN, TRDYN );
inout [31:0] AD;
inout [3:0] CBEN;
input CLK;
inout DEVSELN, FRAMEN;
input GNTN, IDSEL;
output INTAN;
input ir_n;
inout IRDYN;
inout [31:0] lad;
input lclk;
output ld;
output [7:0] led;
output mrs, oe;
input or_n, pae_n, paf_n;
inout PAR, PERRN;
output ren, REQN;
input RSTN;
output SERRN;
inout STOPN, TRDYN;
output wen;
wire [3:0] Usr_CBE;
wire [31:0] Cfg_RdData;
wire [7:0] Cfg_LatCnt;
wire [31:0] Usr_RdData;
wire [31:0] Mst_RdAd;
wire [31:0] Mst_WrAd;
wire [31:0] RdBuff_out;
wire [31:0] WrBuff_in;
wire [31:0] RdBuff_mux;
wire [7:0] ledout;
wire [31:0] Usr_Addr_WrData;
wire [3:0] Mst_BE;
wire [3:0] PCI_Cmd;
wire [3:0] Mst_BE_FIFO;
wire [31:0] Usr_RdDataIn;
wire [31:0] Mst_WrData_Reg;
wire [31:0] Mst_WrData_FIFO;
wire [31:0] Mst_WrData;
wire [31:0] WrD;
wire [7:2] Cfg_CacheLineSize;
wire [7:0] mxledo;
wire [7:0] mxledoi;
wire [9:0] ADR;
wire [15:0] Cfg_CmdReg;
wire N_19;
wire N_15;
wire N_16;
wire N_17;
wire N_18;
wire N_10;
wire N_11;
wire N_12;
wire Mst_LatCntEn;
wire Usr_Last_Cycle_D1;
wire Usr_Stop;
wire N_9;
wire MstSC;
wire N_8;
wire Mst_Data_Sel;
wire N_7;
wire N_6;
wire Mst_BE_Sel;
wire BEFIFO_pop;
wire N_5;
wire BEFIFO_fulln;
wire BEFIFO_emptyn;
wire BEfifo;
wire s1s0;
wire s0en;
wire s1en;
wire ledcntrl;
wire Mst_Rd_Term_Sel;
wire RdBuff_empty_sync;
wire fifo_oe_n;
wire we_out;
wire N_4;
wire DMA_Error;
wire WrBuff_fullN;
wire re_dly;
wire we_int;
wire Cfg_Stop;
wire Prog_Stop;
wire Usr_Rdy;
wire RdBuff_fullN;
wire N_1;
supply1 VCC;
wire Mst_RdData_Valid;
wire ldn;
wire re_out;
wire DMAWrEn;
wire paen_in;
wire fpga_oe;
wire Usr_Write;
wire DMARdEn;
wire Mst_WrData_Valid;
wire WrBuff_almost_full;
wire Mst_Xfer_D1;
wire Mst_Burst_Req;
wire Mst_One_Read;
wire Mst_Two_Reads;
wire RdBuff_almost_empty;
wire local_clock;
wire WrBuff_emptyN;
wire WrBuff_almost_empty;
wire Usr_MstRdAd_Sel;
wire Mst_WrBurst_Done;
wire Usr_MstWrAd_Sel;
wire Mst_RdBurst_Done;
wire Mst_WrData_Rdy;
wire LocalEn;
wire local_reset;
wire loc_sync_reset;
wire Cfg_PERR_Det;
wire Cfg_MstPERR_Det;
wire Cfg_SERR_Sig;
wire Mst_Tabort_Det;
wire Mst_TTO_Det;
wire irn_in;
wire pafn_in;
wire orn_in;
wire RdBuff_empty;
wire RdBuff_full;
wire WrBuff_empty;
wire WrBuff_full;
wire Cfg_Write;
wire Usr_Adr_Valid;
wire Usr_Adr_Inc;
wire Usr_Select;
wire PCI_reset;
wire Usr_RdDecode;
wire PCI_clock;
wire Usr_WrDecode;
supply0 GND;
cfgtaddr_5632_280 I219 ( .Addr_Hit(Usr_Select),
.CacheLineSizeReg({ Cfg_CacheLineSize[7:2] }),
.CBE({ Usr_CBE[3:0] }), .Cfg_Write(Cfg_Write),
.CfgData({ Cfg_RdData[31:0] }),
.CmdReg({ Cfg_CmdReg[15:0] }), .IncrAddr(Usr_Adr_Inc),
.LatTimerReg({ Cfg_LatCnt[7:0] }),
.LoadAddr(Usr_Adr_Valid),
.MstPERR_Det(Cfg_MstPERR_Det), .MstSC(MstSC),
.PCI_clock(PCI_clock), .PCI_reset(PCI_reset),
.PERR_Det(Cfg_PERR_Det), .SERR_Sig(Cfg_SERR_Sig),
.Tabort_Det(Mst_Tabort_Det), .TTO_Det(Mst_TTO_Det),
.Usr_RdCmd(Usr_RdDecode), .Usr_Stop(Cfg_Stop),
.Usr_WrCmd(Usr_WrDecode), .UsrAddr({ ADR[9:0] }),
.WrData({ Usr_Addr_WrData[31:0] }) );
f32a32_25um Rdbuff ( .almostempty(RdBuff_almost_empty),
.din({ RdBuff_mux[31:0] }), .dout({ RdBuff_out[31:0] }),
.empty(RdBuff_empty), .full(RdBuff_full), .pop(we_int),
.push(N_1), .rclk(local_clock), .rrst(loc_sync_reset),
.wclk(PCI_clock), .wrst(local_reset) );
f32a32_25um WrBuff ( .almostempty(WrBuff_almost_empty),
.almostfull(WrBuff_almost_full),
.din({ WrBuff_in[31:0] }),
.dout({ Mst_WrData_FIFO[31:0] }), .empty(WrBuff_empty),
.full(WrBuff_full), .pop(N_6), .push(re_dly),
.rclk(PCI_clock), .rrst(local_reset), .wclk(local_clock),
.wrst(loc_sync_reset) );
pci32_25um I214 ( .AD({ AD[31:0] }), .CBEN({ CBEN[3:0] }),
.Cfg_CacheLineSize({ Cfg_CacheLineSize[7:2] }),
.Cfg_CmdReg3(Cfg_CmdReg[3]), .Cfg_CmdReg4(Cfg_CmdReg[4]),
.Cfg_CmdReg6(Cfg_CmdReg[6]), .Cfg_CmdReg8(Cfg_CmdReg[8]),
.Cfg_LatCnt({ Cfg_LatCnt[7:0] }),
.Cfg_MstPERR_Det(Cfg_MstPERR_Det),
.Cfg_PERR_Det(Cfg_PERR_Det),
.Cfg_RdData({ Cfg_RdData[31:0] }),
.Cfg_SERR_Sig(Cfg_SERR_Sig), .Cfg_Write(Cfg_Write), .CLK(CLK),
.DEVSELN(DEVSELN), .Flush_FIFO(GND), .FRAMEN(FRAMEN),
.GNTN(GNTN), .IDSEL(IDSEL), .IRDYN(IRDYN),
.Mst_BE({ Mst_BE[3:0] }), .Mst_BE_Sel(Mst_BE_Sel),
.Mst_Burst_Req(Mst_Burst_Req), .Mst_LatCntEn(Mst_LatCntEn),
.Mst_One_Read(Mst_One_Read),
.Mst_Rd_Term_Sel(Mst_Rd_Term_Sel),
.Mst_RdAd({ Mst_RdAd[31:0] }),
.Mst_RdBurst_Done(Mst_RdBurst_Done),
.Mst_RdData_Valid(Mst_RdData_Valid),
.Mst_Tabort_Det(Mst_Tabort_Det), .Mst_TTO_Det(Mst_TTO_Det),
.Mst_Two_Reads(Mst_Two_Reads), .Mst_WrAd({ Mst_WrAd[31:0] }),
.Mst_WrBurst_Done(Mst_WrBurst_Done),
.Mst_WrData({ Mst_WrData[31:0] }),
.Mst_WrData_Rdy(Mst_WrData_Rdy),
.Mst_WrData_Valid(Mst_WrData_Valid),
.Mst_Xfer_D1(Mst_Xfer_D1), .PAR(PAR), .PCI_clock(PCI_clock),
.PCI_Cmd({ PCI_Cmd[3:0] }), .PCI_reset(PCI_reset),
.PERRN(PERRN), .REQN(REQN), .RSTN(RSTN), .SERRN(SERRN),
.STOPN(STOPN), .TRDYN(TRDYN), .Usr_Abort(GND),
.Usr_Addr_WrData({ Usr_Addr_WrData[31:0] }),
.Usr_Adr_Inc(Usr_Adr_Inc), .Usr_Adr_Valid(Usr_Adr_Valid),
.Usr_CBE({ Usr_CBE[3:0] }),
.Usr_Last_Cycle_D1(Usr_Last_Cycle_D1),
.Usr_MstRdAd_Sel(Usr_MstRdAd_Sel),
.Usr_MstWrAd_Sel(Usr_MstWrAd_Sel),
.Usr_RdData({ Usr_RdData[31:0] }),
.Usr_RdDecode(Usr_RdDecode), .Usr_Rdy(Usr_Rdy),
.Usr_Select(Usr_Select), .Usr_Stop(Usr_Stop),
.Usr_WrDecode(Usr_WrDecode), .Usr_Write(Usr_Write) );
tripad_25um I170 ( .A(VCC), .EN(GND), .P(INTAN) );
gclkbuff_25um I215 ( .A(fpga_oe), .Z(N_10) );
gclkbuff_25um I187 ( .A(N_16), .Z(loc_sync_reset) );
gclkbuff_25um I188 ( .A(N_15), .Z(local_reset) );
bipadiff_25um \ladpads[31] ( .A2(RdBuff_out[31]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[31]), .P(lad[31]), .Q(WrD[31]) );
bipadiff_25um \ladpads[30] ( .A2(RdBuff_out[30]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[30]), .P(lad[30]), .Q(WrD[30]) );
bipadiff_25um \ladpads[29] ( .A2(RdBuff_out[29]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[29]), .P(lad[29]), .Q(WrD[29]) );
bipadiff_25um \ladpads[28] ( .A2(RdBuff_out[28]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[28]), .P(lad[28]), .Q(WrD[28]) );
bipadiff_25um \ladpads[27] ( .A2(RdBuff_out[27]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[27]), .P(lad[27]), .Q(WrD[27]) );
bipadiff_25um \ladpads[26] ( .A2(RdBuff_out[26]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[26]), .P(lad[26]), .Q(WrD[26]) );
bipadiff_25um \ladpads[25] ( .A2(RdBuff_out[25]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[25]), .P(lad[25]), .Q(WrD[25]) );
bipadiff_25um \ladpads[24] ( .A2(RdBuff_out[24]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[24]), .P(lad[24]), .Q(WrD[24]) );
bipadiff_25um \ladpads[23] ( .A2(RdBuff_out[23]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[23]), .P(lad[23]), .Q(WrD[23]) );
bipadiff_25um \ladpads[22] ( .A2(RdBuff_out[22]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[22]), .P(lad[22]), .Q(WrD[22]) );
bipadiff_25um \ladpads[21] ( .A2(RdBuff_out[21]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[21]), .P(lad[21]), .Q(WrD[21]) );
bipadiff_25um \ladpads[20] ( .A2(RdBuff_out[20]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[20]), .P(lad[20]), .Q(WrD[20]) );
bipadiff_25um \ladpads[19] ( .A2(RdBuff_out[19]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[19]), .P(lad[19]), .Q(WrD[19]) );
bipadiff_25um \ladpads[18] ( .A2(RdBuff_out[18]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[18]), .P(lad[18]), .Q(WrD[18]) );
bipadiff_25um \ladpads[17] ( .A2(RdBuff_out[17]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[17]), .P(lad[17]), .Q(WrD[17]) );
bipadiff_25um \ladpads[16] ( .A2(RdBuff_out[16]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[16]), .P(lad[16]), .Q(WrD[16]) );
bipadiff_25um \ladpads[15] ( .A2(RdBuff_out[15]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[15]), .P(lad[15]), .Q(WrD[15]) );
bipadiff_25um \ladpads[14] ( .A2(RdBuff_out[14]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[14]), .P(lad[14]), .Q(WrD[14]) );
bipadiff_25um \ladpads[13] ( .A2(RdBuff_out[13]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[13]), .P(lad[13]), .Q(WrD[13]) );
bipadiff_25um \ladpads[12] ( .A2(RdBuff_out[12]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[12]), .P(lad[12]), .Q(WrD[12]) );
bipadiff_25um \ladpads[11] ( .A2(RdBuff_out[11]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[11]), .P(lad[11]), .Q(WrD[11]) );
bipadiff_25um \ladpads[10] ( .A2(RdBuff_out[10]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[10]), .P(lad[10]), .Q(WrD[10]) );
bipadiff_25um \ladpads[9] ( .A2(RdBuff_out[9]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[9]), .P(lad[9]), .Q(WrD[9]) );
bipadiff_25um \ladpads[8] ( .A2(RdBuff_out[8]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[8]), .P(lad[8]), .Q(WrD[8]) );
bipadiff_25um \ladpads[7] ( .A2(RdBuff_out[7]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[7]), .P(lad[7]), .Q(WrD[7]) );
bipadiff_25um \ladpads[6] ( .A2(RdBuff_out[6]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[6]), .P(lad[6]), .Q(WrD[6]) );
bipadiff_25um \ladpads[5] ( .A2(RdBuff_out[5]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[5]), .P(lad[5]), .Q(WrD[5]) );
bipadiff_25um \ladpads[4] ( .A2(RdBuff_out[4]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[4]), .P(lad[4]), .Q(WrD[4]) );
bipadiff_25um \ladpads[3] ( .A2(RdBuff_out[3]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[3]), .P(lad[3]), .Q(WrD[3]) );
bipadiff_25um \ladpads[2] ( .A2(RdBuff_out[2]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[2]), .P(lad[2]), .Q(WrD[2]) );
bipadiff_25um \ladpads[1] ( .A2(RdBuff_out[1]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[1]), .P(lad[1]), .Q(WrD[1]) );
bipadiff_25um \ladpads[0] ( .A2(RdBuff_out[0]), .EN(N_10), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_12),
.FFQ(WrBuff_in[0]), .P(lad[0]), .Q(WrD[0]) );
ckpad_25um I189 ( .P(lclk), .Q(local_clock) );
outpad_25um I217 ( .A(N_19), .P(mrs) );
outpad_25um \ledpads[7] ( .A(mxledoi[7]), .P(led[7]) );
outpad_25um \ledpads[6] ( .A(mxledoi[6]), .P(led[6]) );
outpad_25um \ledpads[5] ( .A(mxledoi[5]), .P(led[5]) );
outpad_25um \ledpads[4] ( .A(mxledoi[4]), .P(led[4]) );
outpad_25um \ledpads[3] ( .A(mxledoi[3]), .P(led[3]) );
outpad_25um \ledpads[2] ( .A(mxledoi[2]), .P(led[2]) );
outpad_25um \ledpads[1] ( .A(mxledoi[1]), .P(led[1]) );
outpad_25um \ledpads[0] ( .A(mxledoi[0]), .P(led[0]) );
outpad_25um I201 ( .A(N_18), .P(wen) );
outpad_25um I202 ( .A(N_17), .P(ren) );
outpad_25um I203 ( .A(fifo_oe_n), .P(oe) );
outpad_25um I204 ( .A(ldn), .P(ld) );
inpadff_25um I205 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(irn_in),
.P(ir_n) );
inpadff_25um I207 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(orn_in),
.P(or_n) );
inpadff_25um I208 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(paen_in),
.P(pae_n) );
inpadff_25um I209 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(pafn_in),
.P(paf_n) );
and3i2 I165 ( .A(WrBuff_fullN), .B(fpga_oe), .C(N_11), .Q(N_12) );
dff I166 ( .CLK(local_clock), .D(fpga_oe), .Q(N_11) );
and4i3 I159 ( .A(PCI_Cmd[0]), .B(PCI_Cmd[1]), .C(PCI_Cmd[2]), .D(PCI_Cmd[3]),
.Q(N_8) );
dffe I160 ( .CLK(PCI_clock), .D(N_8), .EN(Mst_Burst_Req), .Q(MstSC) );
and3i1 I157 ( .A(PCI_Cmd[0]), .B(Mst_WrData_Rdy), .C(Mst_Data_Sel), .Q(N_6) );
or3i0 I153 ( .A(N_4), .B(Mst_TTO_Det), .C(N_5), .Q(DMA_Error) );
and2i1 I158 ( .A(Mst_RdData_Valid), .B(Mst_Data_Sel), .Q(N_7) );
and2i1 I154 ( .A(BEFIFO_pop), .B(BEFIFO_emptyn), .Q(N_5) );
f64x4 I151 ( .clk(PCI_clock), .din({ Usr_Addr_WrData[3:0] }),
.dout({ Mst_BE_FIFO[3:0] }), .emptyn(BEFIFO_emptyn),
.fulln(BEFIFO_fulln), .pop(BEFIFO_pop), .push(BEfifo),
.rst(PCI_reset) );
and2i0 I163 ( .A(Mst_WrData_Rdy), .B(Mst_BE_Sel), .Q(BEFIFO_pop) );
and2i0 I147 ( .A(N_1), .B(RdBuff_full), .Q(N_4) );
or2i0 I145 ( .A(Cfg_Stop), .B(Prog_Stop), .Q(Usr_Stop) );
or2i0 I161 ( .A(Usr_Write), .B(Cfg_Write), .Q(N_9) );
mux2x0 \Mst_WrData_Mux[31] ( .A(Mst_WrData_FIFO[31]), .B(Mst_WrData_Reg[31]),
.Q(Mst_WrData[31]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[30] ( .A(Mst_WrData_FIFO[30]), .B(Mst_WrData_Reg[30]),
.Q(Mst_WrData[30]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[29] ( .A(Mst_WrData_FIFO[29]), .B(Mst_WrData_Reg[29]),
.Q(Mst_WrData[29]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[28] ( .A(Mst_WrData_FIFO[28]), .B(Mst_WrData_Reg[28]),
.Q(Mst_WrData[28]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[27] ( .A(Mst_WrData_FIFO[27]), .B(Mst_WrData_Reg[27]),
.Q(Mst_WrData[27]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[26] ( .A(Mst_WrData_FIFO[26]), .B(Mst_WrData_Reg[26]),
.Q(Mst_WrData[26]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[25] ( .A(Mst_WrData_FIFO[25]), .B(Mst_WrData_Reg[25]),
.Q(Mst_WrData[25]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[24] ( .A(Mst_WrData_FIFO[24]), .B(Mst_WrData_Reg[24]),
.Q(Mst_WrData[24]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[23] ( .A(Mst_WrData_FIFO[23]), .B(Mst_WrData_Reg[23]),
.Q(Mst_WrData[23]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[22] ( .A(Mst_WrData_FIFO[22]), .B(Mst_WrData_Reg[22]),
.Q(Mst_WrData[22]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[21] ( .A(Mst_WrData_FIFO[21]), .B(Mst_WrData_Reg[21]),
.Q(Mst_WrData[21]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[20] ( .A(Mst_WrData_FIFO[20]), .B(Mst_WrData_Reg[20]),
.Q(Mst_WrData[20]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[19] ( .A(Mst_WrData_FIFO[19]), .B(Mst_WrData_Reg[19]),
.Q(Mst_WrData[19]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[18] ( .A(Mst_WrData_FIFO[18]), .B(Mst_WrData_Reg[18]),
.Q(Mst_WrData[18]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[17] ( .A(Mst_WrData_FIFO[17]), .B(Mst_WrData_Reg[17]),
.Q(Mst_WrData[17]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[16] ( .A(Mst_WrData_FIFO[16]), .B(Mst_WrData_Reg[16]),
.Q(Mst_WrData[16]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[15] ( .A(Mst_WrData_FIFO[15]), .B(Mst_WrData_Reg[15]),
.Q(Mst_WrData[15]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[14] ( .A(Mst_WrData_FIFO[14]), .B(Mst_WrData_Reg[14]),
.Q(Mst_WrData[14]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[13] ( .A(Mst_WrData_FIFO[13]), .B(Mst_WrData_Reg[13]),
.Q(Mst_WrData[13]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[12] ( .A(Mst_WrData_FIFO[12]), .B(Mst_WrData_Reg[12]),
.Q(Mst_WrData[12]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[11] ( .A(Mst_WrData_FIFO[11]), .B(Mst_WrData_Reg[11]),
.Q(Mst_WrData[11]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[10] ( .A(Mst_WrData_FIFO[10]), .B(Mst_WrData_Reg[10]),
.Q(Mst_WrData[10]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[9] ( .A(Mst_WrData_FIFO[9]), .B(Mst_WrData_Reg[9]),
.Q(Mst_WrData[9]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[8] ( .A(Mst_WrData_FIFO[8]), .B(Mst_WrData_Reg[8]),
.Q(Mst_WrData[8]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[7] ( .A(Mst_WrData_FIFO[7]), .B(Mst_WrData_Reg[7]),
.Q(Mst_WrData[7]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[6] ( .A(Mst_WrData_FIFO[6]), .B(Mst_WrData_Reg[6]),
.Q(Mst_WrData[6]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[5] ( .A(Mst_WrData_FIFO[5]), .B(Mst_WrData_Reg[5]),
.Q(Mst_WrData[5]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[4] ( .A(Mst_WrData_FIFO[4]), .B(Mst_WrData_Reg[4]),
.Q(Mst_WrData[4]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[3] ( .A(Mst_WrData_FIFO[3]), .B(Mst_WrData_Reg[3]),
.Q(Mst_WrData[3]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[2] ( .A(Mst_WrData_FIFO[2]), .B(Mst_WrData_Reg[2]),
.Q(Mst_WrData[2]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[1] ( .A(Mst_WrData_FIFO[1]), .B(Mst_WrData_Reg[1]),
.Q(Mst_WrData[1]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[0] ( .A(Mst_WrData_FIFO[0]), .B(Mst_WrData_Reg[0]),
.Q(Mst_WrData[0]), .S(Mst_Data_Sel) );
mux2x0 \mxled[7] ( .A(WrBuff_full), .B(ledout[7]), .Q(mxledo[7]), .S(ledcntrl) );
mux2x0 \mxled[6] ( .A(WrBuff_empty), .B(ledout[6]), .Q(mxledo[6]), .S(ledcntrl) );
mux2x0 \mxled[5] ( .A(RdBuff_full), .B(ledout[5]), .Q(mxledo[5]), .S(ledcntrl) );
mux2x0 \mxled[4] ( .A(RdBuff_empty), .B(ledout[4]), .Q(mxledo[4]), .S(ledcntrl) );
mux2x0 \mxled[3] ( .A(orn_in), .B(ledout[3]), .Q(mxledo[3]), .S(ledcntrl) );
mux2x0 \mxled[2] ( .A(paen_in), .B(ledout[2]), .Q(mxledo[2]), .S(ledcntrl) );
mux2x0 \mxled[1] ( .A(pafn_in), .B(ledout[1]), .Q(mxledo[1]), .S(ledcntrl) );
mux2x0 \mxled[0] ( .A(irn_in), .B(ledout[0]), .Q(mxledo[0]), .S(ledcntrl) );
dmaregrd I_137 ( .adr({ ADR[9:2] }), .CBE({ Usr_CBE[3:0] }), .clk(PCI_clock),
.clkspd({ s1en,s0en,s1s0 }), .clr(PCI_reset),
.dataout({ Usr_RdDataIn[31:0] }), .DMARdEn(DMARdEn),
.DMAWrEn(DMAWrEn), .IncrAddr(Usr_Adr_Inc),
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -