cardbus_5632_modelsim_post.do

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· DO 代码 · 共 68 行

#------------------------------------------------------------------------------
#
# File : cardbus_5632_modelsim_post.do
# Last Modification: 06/26/2001
#
# Created In SpDE Version: SpDE 9.5.3
# Author : QuickLogic Corporation
# Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
# this file for use in designing with QuickLogic devices only.
#	
# Description :
#	This script runs cardbus_5632 verilog reference design postlayout 
#	simulation in ModelSim.
#	 
# History:	
#	Date	        Author					Version
#	02/05/04		Claire Pian Tu			1.0
#		- Initial.
#
#------------------------------------------------------------------------------


# before running this script you should change your current directory
# in ModelSim to where the simulation files are by using the "cd" command

# cd c:/pasic/design/reference/pci5632_280/verilog
set curpath d:/project/CardBus/Source/verilog

# create work library
vlib work

# compile QuickLogic post-layout primitives
# you might need to add the drive letter to make it look like {c:/pasic/spde/...}
vlog -work work {d:/pasic/spde/data/qlprim.v}

# compile the postlayout netlist
vlog -work work cardbus_5632.vq

# compile test bench files
vlog -work work cardbus_5632.tf

# start simulation with worst-case timing and 100ps resolution
vsim -t 100ps -sdfmax /m=cardbus_5632.sdf work.t
# open a waveform window
view wave
# add PCI signals
add wave /t/PERRN
add wave /t/SERRN
add wave /t/PAR
add wave /t/REQN
add wave /t/GNTN
add wave /t/RSTN
add wave /t/CLK
add wave /t/IDSEL
add wave -format Literal -radix hexadecimal /t/AD(31:0)
add wave -format Literal -radix hexadecimal /t/CBEN(3:0)
add wave /t/FRAMEN
add wave /t/IRDYN
add wave /t/DEVSELN
add wave /t/TRDYN
add wave /t/STOPN

# run simulation till end
onbreak resume
run -all
#write transcript pci5632_280post.doc
#quit -f