cardbus_wrapper.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 829 行 · 第 1/3 页

	@(posedge CLK);

	if (!pad_clk_stopped)
		$display("CLK MGMT Test #2 - pad_clk_stopped = 0 ... PASSED.");
	else
		$display("CLK MGMT Test #2 - pad_clk_stopped = 1 ... FAILED.");

		// clk_cnt =0 --> 1
    tb_clkrun_n <= 1'b1;
	repeat (1) @(posedge CLK);

	if (!pad_clk_stopped)
		$display("CLK MGMT Test #3 - pad_clk_stopped = 0 ... PASSED.");
	else
		$display("CLK MGMT Test #3 - pad_clk_stopped = 1 ... FAILED.");

	// clk_cnt = 1-->2
	repeat (1) @(posedge CLK);

	// clk_cnt =2 
	tb_clkrun_oe <= 1'b0;
	tb_clkrun_n <= 1'b0;
	@(posedge CLK);

	if (pad_clk_stopped)
		$display("CLK MGMT Test #4 - pad_clk_stopped = 1 ... PASSED.");
	else
		$display("CLK MGMT Test #4 - pad_clk_stopped = 0 ... FAILED.");
	$display("Clock Management Test#4 finished at %0d", $time);

	// clk resume for one clock cycle
	// same as tb_clkrun_oe <= 1'b1 & tb_clkrun_n <= 1'0;
	// clk_cnt =2 --> 3
	pad_clk_resume <= 1'b1;

	@(posedge CLK);

	if (pad_clk_stopped)
		$display("CLK MGMT Test #5 - pad_clk_stopped = 1 ... PASSED.");
	else
		$display("CLK MGMT Test #5 - pad_clk_stopped = 0 ... FAILED.");

	// clk_cnt =3 --> 2
	pad_clk_resume <= 1'b0;
	// same as tb_clk_run_n <= 1'b1;
	@(posedge CLK);
	
	//so set up for the next state and then check the current test case

	if (pad_clk_stopped)
		$display("CLK MGMT Test #6 - pad_clk_stopped = 1 ... PASSED.");
	else
		$display("CLK MGMT Test #6 - pad_clk_stopped = 0 ... FAILED.");

	// clk_cnt =2 --> 3
	pad_clk_resume <= 1'b1;
	// same as tb_clk_run_n <= 1'b0;
	@(posedge CLK);

	if (pad_clk_stopped)
		$display("CLK MGMT Test #7 - pad_clk_stopped = 1 ... PASSED.");
	else
		$display("CLK MGMT Test #7 - pad_clk_stopped = 0 ... FAILED.");

	// clk_cnt = 3 --> 0
	pad_clk_resume <= 1'b1;
	@(posedge CLK);

	if (pad_clk_stopped)
		$display("CLK MGMT Test #8 - pad_clk_stopped = 1 ... PASSED.");
	else
		$display("CLK MGMT Test #8 - pad_clk_stopped = 0 ... FAILED.");
	$display("Clock Management Test#8 finished at %0d", $time);
	// clk resume for two clock cycles to resume the clock
	// clk_cnt =3 --> 0
	pad_clk_resume <= 1'b0;
  	tb_clkrun_oe <= 1'b1;
 	tb_clkrun_n <= 1'b0;

    repeat (1) @(posedge CLK);
//	@(posedge CLK);
  //	#HalfCyclePCI;
	// return to normal
	if (!pad_clk_stopped)
		$display("CLK MGMT Test #9 - pad_clk_stopped = 0 ... PASSED.");
	else
		$display("CLK MGMT Test #9 - pad_clk_stopped = 1 ... FAILED.");
	$display("Clock Management Test#9 finished at %0d", $time);
	
	



	// --------------------------------------------------------//
	$display("\n\nTest CardBus Locked Transfers at %0d\n", $time);
	$display("\nIRDY protocol errors expected (2x)");
	// --------------------------------------------------------//
	//signal lock xfer, check lock detect
	//access as owner, check result.
	//access by non owner, check result
	//signal unlock, check result


	/* 	Test Locked Transfer - Test 1
		- unlocked, and not target of access
		- should not respond to access
	*/

	// unlock and check result
	pad_CBLOCK_n <= 1'b1;
	// target should be unlocked and owner_access should be 0					
	master_2.target_access_pf(32'hAB000000 + EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	@(posedge CLK);

	if (pad_locked || pad_owner_access)
		$display("Locked Transfers Test 1 - pad_locked or pad_owner_access = 1 ... FAILED.");
	else
		$display("Locked Trasnfers Test 1 ... PASSED.");
	
	/* 	Test Locked Transfer - Test 2
		- unlocked, target of access but do not lock
		- locked and owner_access should be deasserted
	*/

	// unlock and check result
	pad_CBLOCK_n <= 1'b1;
	// target should be unlocked and owner_access should be 0					
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	@(posedge CLK);

	if (pad_locked || pad_owner_access)
		$display("Locked Transfers Test 2 - pad_locked or pad_owner_access = 1 ... FAILED.");
	else
		$display("Locked Trasnfers Test 2 ... PASSED.");

	/* 	Test Locked Transfer - Test 3
		- unlocked, access exclusively
		- locked and owner_access should both be asserted
	*/

  	fork:  Test3   //send control pulse to both begin-ends 
  	   begin 
	     //do the memory access - clear event notice -
		master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
		@(posedge CLK);
           end 
	   begin 
	         //change value of CBLOCK# 
		repeat (1) @(posedge CLK);
		@(negedge CLK);
		pad_CBLOCK_n <= 1'b0;
		   end 
	join

	if (pad_locked)
		$display("Locked Transfers Test #3a - pad_locked = 1 ... PASSED.");
	else
		$display("Locked Transfers Test #3a - pad_locked = 0 ... FAILED.");		

	@(posedge CLK);

	if (pad_owner_access)
		$display("Locked Transfers Test #3b - pad_owner_access = 1 ... PASSED.");
	else
		$display("Locked Transfers Test #3b - pad_owner_access = 0 ... FAILED.");

	/* 	Test Locked Transfer - Test 4
		- locked, access by owner
		- locked should be asserted and owner_access should be asserted
	*/	  

  	fork: Test4    //send control pulse to both begin-ends 
  	   begin 
	     //do the memory access - clear event notice -
		repeat (2) @(posedge CLK);
		master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

           end 
	   begin 
	         //change value of CBLOCK# 
	   	@(posedge CLK);
		pad_CBLOCK_n <= 1'b1;
		repeat (2) @(posedge CLK);
		@(negedge CLK);
		pad_CBLOCK_n <= 1'b0;
		   end 
	join

	if (pad_locked)
		$display("Locked Transfers Test #4a - pad_locked = 1 ... PASSED.");
	else
		$display("Locked Transfers Test #4a - pad_locked = 0 ... FAILED.");		

	@(posedge CLK);

	if (pad_owner_access)
		$display("Locked Transfers Test #4b - pad_owner_access = 1 ... PASSED.");
	else
		$display("Locked Transfers Test #4b - pad_owner_access = 0 ... FAILED.");

	/* 	Test Locked Transfer - Test 5
		- locked, access by non-owner
		- locked should be asserted and owner_access should not be asserted
	*/

	// do another memory access
	// target should remained locked and owner_access should be 0					
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	@(posedge CLK);

	if (pad_locked)
		$display("Locked Transfers Test #5a - pad_locked = 1 ... PASSED.");
	else
		$display("Locked Transfers Test #5a - pad_locked = 0 ... FAILED.");		

	@(posedge CLK);

	if (!pad_owner_access)
		$display("Locked Transfers Test #5b - pad_owner_access = 0 ... PASSED.");
	else
		$display("Locked Transfers Test #5b - pad_owner_access = 1 ... FAILED.");


	/* 	Test Locked Transfer - Test 6
		- locked, not target of access
		- locked should be asserted and owner_access should not be asserted
	*/

	// target should be locked and owner_access should be 0					
	master_2.target_access_pf(32'hAB000000 + EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	@(posedge CLK);

	if (pad_locked)
		$display("Locked Transfers Test #6a - pad_locked = 1 ... PASSED.");
	else
		$display("Locked Transfers Test #6a - pad_locked = 0 ... FAILED.");

	@(posedge CLK);

	if (!pad_owner_access)
		$display("Locked Transfers Test #6b - pad_owner_access = 0 ... PASSED.");
	else
		$display("Locked Transfers Test #6b - pad_owner_access = 1 ... FAILED.");

	// unlock
   	@(posedge CLK);
	pad_CBLOCK_n <= 1'b1;

	// --------------------------------------------------------//
	$display("\n\nTest CardBus CIS at %0d\n", $time);
	// --------------------------------------------------------//
	master_2.target_access_pf(CardBus_BAR+CIS_OFFSET_0,32'h04030201,MEM_READ,8'hFF,1'b0,1'b0,1,0,0,1'b0, pass, 1'b0); 

	@(posedge CLK);

	master_2.target_access_pf(CardBus_BAR+CIS_OFFSET_1,32'h08070605,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

	@(posedge CLK);

	master_2.target_access_pf(CardBus_BAR+CIS_OFFSET_2,32'h0C0B0A09,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

	@(posedge CLK);

	master_2.target_access_pf(CardBus_BAR+CIS_OFFSET_3,32'h100F0E0D,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 						

	@(posedge CLK);

	master_2.target_access_pf(CardBus_BAR+CIS_OFFSET_4,32'h22000000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

repeat (5) @(posedge CLK);
$display("\nCardBus Wrapper Test Bench Finished!!!\n");
//$stop;