cardbus_wrapper.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 829 行 · 第 1/3 页

TF
829 行
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123
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h801F,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (!pad_CSTSCHG)
		$display("...Event#3 forced and CSTSCHG not asserted, PASSED");
	else begin
		$display("...CSTSCHG asserted, FAILED!!!!!!!!!!!");
		$stop;
	end



	//write to present state and event reg, read to make sure didn't change
	$display("Test Invalid Writes to Function Event and State Registers at %0d", $time);
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15
	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b1;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b1;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b1;		// bit 15
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h000A,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h800A,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// write 0 to event register (should have no effect)
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// write to present state register (should have no effect)
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h12345678,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h000A,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h800A,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	$display("...PASSED");

	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

	/* ctu notes -------
	Test CardBus Interrupt Events (4)
	Test 1: Enable Intr, set intr_ps high, CINT_n should be asserted
	Test 2: Enable Intr, force intr function event high, CINT_n should be asserted
	Test 3: Disable Intr, set intr_ps high, CINT_n should NOT be asserted
	Test 4: Disable Intr, force intr function event high, CINT_n should NOT be asserted
	------- */

	// --------------------------------------------------------//
	$display("\n\nTest CardBus Interrupt at %0d\n\n", $time);
	// --------------------------------------------------------//
	//enable INTR, toggle present state intr requests, check interrupt
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15
	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	// write to mask offset, enable INTR and disable everything else
	$display("Mask all events except INTR at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h8000,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	$display("Change present state pad_intr input at %0d", $time);
	pad_intr <= 1'b1;		// bit 15
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h8000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	if (!pad_CINT_n)
		$display("Interrupt Test #1 - pad_CINT_n asserted ... PASSED.");
	else
		$display("Interrupt Test #1 - pad_CINT_n not asserted ... FAILED.");



	//enable INTR, force intr requests, check interrupt
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15

	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	// write to force event register
	$display("Force INTR event at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+FORCE_OFFSET,32'h8000,MEM_WRITE,8'hF8,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h8000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h0000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	if (!pad_CINT_n)
		$display("Interrupt Test #2 - pad_CINT_n asserted ... PASSED.");
	else
		$display("Interrupt Test #2 - pad_CINT_n not asserted ... FAILED.");



	//disable INTR, toggle intr requests, check interrupt
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15
	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	// write to mask offset, disable everything
	$display("Mask all events at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h0000,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	$display("Change present state pad_intr input at %0d", $time);
	pad_intr <= 1'b1;		// bit 15
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h8000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	if (pad_CINT_n)
		$display("Interrupt Test #3 - pad_CINT_n not asserted ... PASSED.");
	else
		$display("Interrupt Test #3 - pad_CINT_n asserted ... FAILED.");



	// force intr requests, check interrupt
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15

	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	// write to force event register
	$display("Force INTR event at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+FORCE_OFFSET,32'h8000,MEM_WRITE,8'hF8,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h8000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h0000,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

	if (pad_CINT_n)
		$display("Interrupt Test #4 - pad_CINT_n not asserted ... PASSED.");
	else
		$display("Interrupt Test #4 - pad_CINT_n asserted ... FAILED.");	

	// --------------------------------------------------------//
	$display("\n\nTest CardBus Audio at %0d\n", $time);
	// --------------------------------------------------------//
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);

    //supply BAM and PWM
    pad_BAM <= 1'b0;
	pad_PWM <= 1'b1;

	//disable both, check CAUDIO_n, should be inactive -> low
	// write to mask offset, disable everything
	$display("Mask all events, disable BAM and PWM at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h0000,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (!pad_CAUDIO)
		$display("CAUDIO Test #1 - pad_CAUDIO not asserted ... PASSED.");
	else
		$display("CAUDIO Test #1 - pad_CAUDIO asserted ... FAILED.");	

	//enable both, check CAUDIO_n, should be inactive -> low
	// write to mask offset, enable bit 5 and 6
	$display("Enable BAM and PWM at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h0060,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (!pad_CAUDIO)
		$display("CAUDIO Test #2 - pad_CAUDIO not asserted ... PASSED.");
	else
		$display("CAUDIO Test #2 - pad_CAUDIO asserted ... FAILED.");	

	//enable only BAM, check CAUDIO
	// write to mask offset, enable bit 5, BAM
	$display("Enable BAM at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h0020,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (!pad_CAUDIO)
		$display("CAUDIO Test #3a - pad_CAUDIO = pad_BAM ... PASSED.");
	else
		$display("CAUDIO Test #3a - pad_CAUDIO != pad_BAM ... FAILED.");	

    pad_BAM <= 1'b1;
	pad_PWM <= 1'b0;	
	repeat (2) @(posedge CLK);
	if (pad_CAUDIO)
		$display("CAUDIO Test #3b - pad_CAUDIO = pad_BAM ... PASSED.");
	else
		$display("CAUDIO Test #3b - pad_CAUDIO != pad_BAM ... FAILED.");	

	//enable only PWM, check CAUDIO
	// write to mask offset, enable bit 6, PWM
	$display("Enable PWM at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h0040,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (!pad_CAUDIO)
		$display("CAUDIO Test #4a - pad_CAUDIO = pad_PWM ... PASSED.");
	else
		$display("CAUDIO Test #4a - pad_CAUDIO != pad_PWM ... FAILED.");	

    pad_BAM <= 1'b0;
	pad_PWM <= 1'b1;
	repeat (2) @(posedge CLK);
	if (pad_CAUDIO)
		$display("CAUDIO Test #4b - pad_CAUDIO = pad_PWM ... PASSED.");
	else
		$display("CAUDIO Test #4b - pad_CAUDIO != pad_PWM ... FAILED.");	


	// --------------------------------------------------------//
	$display("\n\nTest CardBus Clock Management at %0d\n", $time);
	// --------------------------------------------------------//
	//signal stop clock
	//resume request after stopped, check CCLKRUN, supply clock
	//signal stop clock
	//resume request before stopped, check CCLKRUN, supply clock

	if (!pad_clk_stopped)
		$display("CLK MGMT Test #1 - pad_clk_stopped = 0 ... PASSED.");
	else
		$display("CLK MGMT Test #1 - pad_clk_stopped = 1 ... FAILED.");

	// signal stop clock
	// clk_cnt =0 --> 1
	//#2
//	@(negedge CLK);
	@(posedge CLK);
	tb_clkrun_oe <= 1'b1;
	tb_clkrun_n <= 1'b1;
//	@(negedge CLK);
	//repeat (10) @(posedge CLK);
	repeat (1) @(posedge CLK);

// need to shift and interleave the tests and the actual set up of values
 //	@(negedge CLK);
	// clk_cnt =1 --> 0
	tb_clkrun_n <= 1'b0;
   //	@(negedge CLK);
123

cardbus_wrapper.tf - 源码说明

本页面展示了「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」中的 cardbus_wrapper.tf 源码文件，采用 TF 编程语言编写，共 829 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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