cardbus_wrapper.tf

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TF 代码 · 共 829 行 · 第 1/3 页

TF
829 行
字号
123
	/*
	task target_access_pf(address, data, command, be, addr_parity,
                   data_parity, dword_count, initial_data_delay,
                   next_data_delay, m64bit, pass_fail, quiet);
	*/
	// DS added TEST CARDBUS FUNCTIONS
	$display("\n\nTest CardBus Wrapper Module at %0d\n\n", $time);
	//`include "cardbus_wrapper_test.tf"
	// --------------------------------------------------------//
	$display("\nTest Function Event Registers at %0d\n", $time);
	// --------------------------------------------------------//
	//read default values

	$display("Reading default values of all CSTSCHG-related registers at %0d", $time);	
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15

	repeat (5) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	// read event mask register
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h0,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h0,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	// read force event register
	master_2.target_access_pf(CardBus_BAR+FORCE_OFFSET,32'h0,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

	repeat (5) @(posedge CLK);
	$display("Enabling all event sources for CSTSCHG generation at %0d", $time);
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hFFFFFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 

	/* ctu-------------------------
	CHANGE FIRST 3 BITS TO 1
	SO STATUS CHANGED SHOULD SHOW 1 
	AND PRESENT STATE IS ALSO 1
	---------------------------- */

	//change present state, read state and event, write to clear, read
	repeat (5) @(posedge CLK);
	$display("Toggling state inputs at %0d", $time);
	pad_wp <= 1'b1;			// bit 0
	pad_ready <= 1'b1;		// bit 1
	pad_bvd[2] <= 1'b1;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15
	repeat (5) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0007,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h0007,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	if (pad_CSTSCHG)
		$display("...CSTSCHG asserted, PASSED");
	else begin
		$display("...CSTSCHG not asserted, FAILED!!!!!!!!!!!");
		$stop;
	end
	$display("Clearing status change event notice...");
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	if (!pad_CSTSCHG)
		$display("...CSTSCHG cleared, PASSED");
	else begin
		$display("...CSTSCHG not cleared, FAILED!!!!!!!!!!!");
		$stop;
	end

	/* ctu-------------------------
	CHANGE FIRST 3 BITS TO 0
	SO STATUS CHANGED SHOULD SHOW 1 
	AND PRESENT STATE IS 0
	---------------------------- */

	repeat (5) @(posedge CLK);
	$display("Toggling state inputs at %0d", $time);
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b1;		// bit 3
	pad_gwake <= 1'b1;		// bit 4
	pad_intr <= 1'b1;		// bit 15
	repeat (5) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h001F,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h8018,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	if (pad_CSTSCHG)
		$display("...CSTSCHG asserted, PASSED");
	else begin
		$display("...CSTSCHG not asserted, FAILED!!!!!!!!!!!");
		$stop;
	end
	$display("Clearing status change event notice...");
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	if (!pad_CSTSCHG)
		$display("...CSTSCHG cleared, PASSED");
	else begin
		$display("...CSTSCHG not cleared, FAILED!!!!!!!!!!!");
		$stop;
	end

	/* ctu notes -------
	Test Event Function and Mask Register Events (6)
	------- */

	//enable and disable WKUP, change states, check event and interrupt
	pad_wp <= 1'b0;			// bit 0
	pad_ready <= 1'b0;		// bit 1
	pad_bvd[2] <= 1'b0;		// bit 2
	pad_bvd[1] <= 1'b0;		// bit 3
	pad_gwake <= 1'b0;		// bit 4
	pad_intr <= 1'b0;		// bit 15
	repeat (5) @(posedge CLK);
	$display("Masking event sources for CSTSCHG generation at %0d", $time);
	// enable WKUP and all sources
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hCFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0018,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h0,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (5) @(posedge CLK);
	if (pad_CSTSCHG)
		$display("...Event#1 detected and CSTSCHG asserted, PASSED");
	else begin
		$display("...CSTSCHG not asserted, FAILED!!!!!!!!!!!");
		$stop;
	end
	// disable WKUP (CSTSCHG will not be flagged)
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h8FFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	if (!pad_CSTSCHG)
		$display("...Event#2 detected and CSTSCHG not asserted, PASSED");
	else begin
		$display("...CSTSCHG asserted, FAILED!!!!!!!!!!!");
		$stop;
	end

	//write to mask, change present states, read to make sure updated but no interrupt
	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	pad_wp <= 1'b1;			// bit 0 event
	repeat (2) @(posedge CLK);
	// enable WKUP and enable all but WP
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hC01E,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h1,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h1,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	if (!pad_CSTSCHG)
		$display("...Event#3 detected and CSTSCHG not asserted, PASSED");
	else begin
		$display("...CSTSCHG asserted, FAILED!!!!!!!!!!!");
		$stop;
	end

	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	pad_ready <= 1'b1;		// bit 1 event
	repeat (2) @(posedge CLK);
	// enable WKUP and enable all but READY
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hC01D,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h2,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h3,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	if (!pad_CSTSCHG)
		$display("...Event#4 detected and CSTSCHG not asserted, PASSED");
	else begin
		$display("...CSTSCHG asserted, FAILED!!!!!!!!!!!");
		$stop;
	end

	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	pad_bvd[2:1] <= 2'b01;		// bit 2/3 event
	repeat (2) @(posedge CLK);
	// enable WKUP and enable all but BVD
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hC013,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h8,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'hB,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	if (!pad_CSTSCHG)
		$display("...Event#5 detected and CSTSCHG not asserted, PASSED");
	else begin
		$display("...CSTSCHG asserted, FAILED!!!!!!!!!!!");
		$stop;
	end

	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	pad_gwake <= 1'b1;		// bit 4 event
	repeat (2) @(posedge CLK);
	// enable WKUP and enable all but GWAKE
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hC00F,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h10,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read present state register
	master_2.target_access_pf(CardBus_BAR+STATE_OFFSET,32'h1B,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	if (!pad_CSTSCHG)
		$display("...Event#6 detected and CSTSCHG not asserted, PASSED");
	else begin
		$display("...CSTSCHG asserted, FAILED!!!!!!!!!!!");
		$stop;
	end

	/* ctu notes -------
	Test Force Function Events (3)
	------- */

	//enable and disable WKUP, force states, check event and interrupt
	$display("Force Function Events at %0d", $time);
	repeat (2) @(posedge CLK);
	// clear event notice
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'hFFFF,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// enable WKUP and all sources
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'hC01F,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// force events
	master_2.target_access_pf(CardBus_BAR+FORCE_OFFSET,32'h0011,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h0011,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (pad_CSTSCHG)
		$display("...Event#1 forced and CSTSCHG asserted, PASSED");
	else begin
		$display("...CSTSCHG not asserted, FAILED!!!!!!!!!!!");
		$stop;
	end
	repeat (2) @(posedge CLK);
	// force events
	master_2.target_access_pf(CardBus_BAR+FORCE_OFFSET,32'h8007,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
	master_2.target_access_pf(CardBus_BAR+EVENT_OFFSET,32'h8017,MEM_READ,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	if (pad_CSTSCHG)
		$display("...Event#2 forced and CSTSCHG asserted, PASSED");
	else begin
		$display("...CSTSCHG not asserted, FAILED!!!!!!!!!!!");
		$stop;
	end
	repeat (2) @(posedge CLK);
	// disable WKUP and enable all sources
	master_2.target_access_pf(CardBus_BAR+MASK_OFFSET,32'h801F,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// force events
	master_2.target_access_pf(CardBus_BAR+FORCE_OFFSET,32'h8,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0, pass, 1'b0); 
	repeat (2) @(posedge CLK);
	// read event register
123

cardbus_wrapper.tf - 源码说明

本页面展示了「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」中的 cardbus_wrapper.tf 源码文件，采用 TF 编程语言编写，共 829 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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