📄 ct_single_r_w.tf
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//------------------------------------------------------------------------------
//
// File : ct_single_r_w.tf
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author : Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//
// Description :
// This file implements the master single read/write tests of the PCI compliance
// test suite to test the QL5332-33/QL5432-33 devices in their reference designs.
//
// Hierarchy:
// This file is to be included by ct_master.tf.
//
// History:
// Date Author Version
// 06/26/01 Richard Yuan 1.0
// - Header added to conform to coding standard.
//
//------------------------------------------------------------------------------
// Master Single Read and Write to a Target Test
// enable bus master and clear status bits
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
if (mem) begin
// write test pattern to location 0 in Target
repeat (5) @(posedge CLK);
master_2.target_access(32'h11110000,64'hABCDEFAB,MEM_WRITE,8'hFF,0,0,1,1,1,0);
// clear test pattern at location 8000 in Target
repeat (5) @(posedge CLK);
master_2.target_access(32'h11118000,64'h00000000,MEM_WRITE,8'hFF,0,0,1,1,1,0);
// Configure and enable a 1 cycle DMA read from the Target
master_2.data_array[0] = 32'h00010001;
if (slower_than_subtractive) begin
master_2.data_array[1] = 32'h11128000 >> 2;
master_2.data_array[2] = 32'h11120000 >> 2;
end else begin
master_2.data_array[1] = 32'h11118000 >> 2;
master_2.data_array[2] = 32'h11110000 >> 2;
end
master_2.data_array[3] = 32'hC1000000;
end else if (io) begin
// write test pattern to location 0 in Target
repeat (5) @(posedge CLK);
master_2.target_access(32'h01110000,64'hABCDEFAB,IO_WRITE,8'hFF,0,0,1,1,1,0);
// clear test pattern at location 80 in Target
repeat (5) @(posedge CLK);
master_2.target_access(32'h01110080,64'h00000000,IO_WRITE,8'hFF,0,0,1,1,1,0);
// Configure and enable a 1 cycle DMA read from the Target
master_2.data_array[0] = 32'h00010001;
if (slower_than_subtractive) begin
master_2.data_array[1] = 32'h01120080 >> 2;
master_2.data_array[2] = 32'h01120000 >> 2;
end else begin
master_2.data_array[1] = 32'h01110080 >> 2;
master_2.data_array[2] = 32'h01110000 >> 2;
end
master_2.data_array[3] = {8'b11_1001_01,24'h000000};
end else if (cfg) begin
// write test pattern to location 0 in Target
force m.IDSEL = 1'b0; // force QL part not to respond
repeat (5) @(posedge CLK);
master_2.target_access(32'h40000000,64'hABCDEFAB,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
// clear test pattern at location 80 in Target
repeat (5) @(posedge CLK);
master_2.target_access(32'h40000080,64'h00000000,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
release m.IDSEL;
// Configure and enable a 1 cycle DMA read from the Target
master_2.data_array[0] = 32'h00010001;
if (slower_than_subtractive) begin
master_2.data_array[1] = 32'h20000080 >> 2;
master_2.data_array[2] = 32'h20000000 >> 2;
end else begin
master_2.data_array[1] = 32'h40000080 >> 2;
master_2.data_array[2] = 32'h40000000 >> 2;
end
master_2.data_array[3] = {8'b11_1101_01,24'h000000};
end else if (ia) begin
// Configure and enable a 1 cycle DMA read from the Target
master_2.data_array[0] = 32'h00010001;
master_2.data_array[1] = 32'h00000000 >> 2;
master_2.data_array[2] = 32'h00000000 >> 2;
master_2.data_array[3] = {8'b11_1000_01,16'h0000,8'b10000000};
end
if (single_target_abort) target_1.TARGET_ABORT = 1;
if (single_retry) begin
target_1.STOP_ENABLE = 1; //Enable/Disable stop assertion
target_1.RETRY_COUNT = 1; //# of retries to force before disabling stop assertion
end
if (single_disconnect) target_1.STOP_ENABLE = 1;
for (i = 0; i < 5; i = i + 1) begin
master_2.be_array[i] = 4'hF;
end
repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,4,1,1,0);
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
repeat (20) @(posedge CLK);
master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
if (master_2.data_read[25:24] == 2'b00) begin
$display("\tMaster DMA Completed Successfully at %0d", $time);
i = 300;
end
if (master_2.data_read[25:24] == 2'b10) begin
$display("\tMaster DMA did not complete at %0d", $time);
i = 300;
end
end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout) at %0d", $time);
target_1.TARGET_ABORT = 0;
target_1.STOP_ENABLE = 0; //Enable/Disable stop assertion
target_1.RETRY_COUNT = 0; //# of retries to force before disabling stop assertion
if (slower_than_subtractive) begin
// Check Master Abort status bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[29] == 1)
$display("\tMaster Abort Status Bit Set ... Passed");
else $display("\tMaster Abort Status Bit Not Set ... Failed");
// enable bus master and clear status bits
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
end
if (single_target_abort) begin
// Check Target Abort status bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[28] == 1)
$display("\tTarget Abort Status Bit Set ... Passed");
else $display("\tTarget Abort Status Bit Not Set ... Failed");
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
// enable bus master and clear status bits
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
end
if (~ia) begin
if (slower_than_subtractive || single_target_abort) begin
// write test pattern to location 0 in Target
repeat (5) @(posedge CLK);
master_2.target_access(32'h11110000,64'hABCDEFAB,MEM_WRITE,8'hFF,0,0,1,1,1,0);
// repeat DMA but address correct target this time (puts one DWORD into Master's FIFD)
master_2.data_array[0] = 32'h11110000 >> 2; // not used
master_2.data_array[1] = 32'hC1000000; // not used
repeat (5) @(posedge CLK);
master_2.target_access(32'h22000108,{32'hC1000000,32'h04444000},MEM_WRITE,8'hFF,0,0,2,1,1,0);
for (i = 0; i < 20; i = i + 1) begin
repeat (20) @(posedge CLK);
master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
if (master_2.data_read[25:24] == 2'b00) begin
$display("\tMaster DMA Completed Successfully at %0d", $time);
i = 300;
end
if (master_2.data_read[25:24] == 2'b10) begin
$display("\tMaster DMA did not complete at %0d", $time);
i = 300;
end
end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout) at %0d", $time);
repeat (5) @(posedge CLK);
end
if (single_target_abort) target_1.TARGET_ABORT = 1;
if (single_retry) begin
target_1.STOP_ENABLE = 1; //Enable/Disable stop assertion
target_1.RETRY_COUNT = 1; //# of retries to force before disabling stop assertion
end
if (single_disconnect) target_1.STOP_ENABLE = 1;
repeat (5) @(posedge CLK);
if (mem) begin
master_2.target_access(32'h2200010C,64'hC0000100,MEM_WRITE,8'hFF,0,0,1,1,1,0);
end
if (io) begin
master_2.target_access(32'h2200010C,{32'h0,16'hC000,8'b00_0_001_01,8'h00},MEM_WRITE,8'hFF,0,0,1,1,1,0);
end
if (cfg) begin
master_2.target_access(32'h2200010C,{32'h0,16'hC000,8'b00_0_101_01,8'h00},MEM_WRITE,8'hFF,0,0,1,1,1,0);
end
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
repeat (20) @(posedge CLK);
master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
if (master_2.data_read[9:8] == 2'b00) begin
$display("\tMaster DMA Completed Successfully at %0d", $time);
i = 300;
end
if (master_2.data_read[9:8] == 2'b10) begin
$display("\tMaster DMA did not complete at %0d", $time);
i = 300;
end
end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout) at %0d", $time);
target_1.TARGET_ABORT = 0;
target_1.STOP_ENABLE = 0; //Enable/Disable stop assertion
target_1.RETRY_COUNT = 0; //# of retries to force before disabling stop assertion
if (slower_than_subtractive) begin
// Check Master Abort status bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[29] == 1)
$display("\tMaster Abort Status Bit Set ... Passed");
else $display("\tMaster Abort Status Bit Not Set ... Failed");
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
end
if (single_target_abort) begin
// Check Target Abort status bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[28] == 1)
$display("\tTarget Abort Status Bit Set ... Passed");
else $display("\tTarget Abort Status Bit Not Set ... Failed");
// enable bus master and clear status bits
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
end
end
if (~single_target_abort && ~slower_than_subtractive) begin
if (mem) begin
// read test pattern from location 8000 in Target
$display("\tComparing Data at Target Location 0 with Target Location 0x8000");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h11118000,32'hABCDEFAB,MEM_READ,8'hFF,0,0,1,1,1,0, pass, 0);
end else if (io) begin
// read test pattern from location 80 in Target
$display("\tComparing Data at Target Location 0 with Target Location 0x80");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h01110080,32'hABCDEFAB,IO_READ,8'hFF,0,0,1,1,1,0, pass, 0);
end else if (cfg) begin
// read test pattern from location 80 in Target
$display("\tComparing Data at Target Location 0 with Target Location 0x80");
force m.IDSEL = 1'b0;
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h40000080,32'hABCDEFAB,CONFIG_READ,8'hFF,0,0,1,1,1,0, pass, 0);
release m.IDSEL;
end else if (ia) begin
// read test pattern from location 11C in QL part
$display("\tComparing Data");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h2200011C,32'h78787878,MEM_READ,8'hFF,0,0,1,1,1,0, pass, 0);
// clear FIFO
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200010C,32'h00000000,MEM_WRITE,8'hFF,0,0,1,1,1,0);
end
if ((target_1.DEVICE_SPEED == 2'b11) // Subtractive decode target
|| single_retry) begin // single retry
// Check Master Abort status bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[29] == 1)
$display("\tMaster Abort Status Bit Set ... Failed");
else $display("\tMaster Abort Status Bit Not Set ... Passed");
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
end
end
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