cardbus_5632.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

`ifdef frag_m
`else
`define frag_m
module frag_m( B1 , B2, C1, C2, D1, D2, E1, E2, NS, OS, NZ, OZ );
input B1, B2, C1, C2, D1, D2, E1, E2, NS;
output NZ;
input OS;
output OZ;
parameter ql_frag = 1;
 assign #1 NZ = NS ? (E1 & ~E2):(D1 & ~D2);
 assign #1 OZ = OS ? NZ:(NS ? (C1 & ~C2):(B1 & ~B2));

endmodule // frag_m

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter ql_frag = 1;
 wire EQMUX_Z, OQMUX_Z; 
 reg EQZ, OQQ, IQQ; 
 assign #1 EQMUX_Z = ESEL ? IE : EQZ; 
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ; 
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz; 
 assign #1 IZ = IP; 

  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      EQZ <= #1 1'b0;
    else if (EQE)
      EQZ <= #1 IE; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      IQQ <= #1 1'b0; 
    else if (IQE) 
      IQQ <= #1 IP; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR) 
      OQQ <= #1 1'b0; 
    else 
      OQQ <= #1 OQI; 

endmodule // eio_cell

`endif

`ifdef afifoflg
`else
`define afifoflg
module afifoflg( clk , holdoff, one, reset, rw, set, two, zero, almost_on,
                 flag_on );
output almost_on;
input clk;
output flag_on;
input holdoff, one, reset, rw, set, two, zero;
wire N_10;
wire N_8;
wire N_9;
wire zero_r1;
wire N_1;
wire N_3;
wire nzeronone;
wire nzeronone_r1;
wire N_4;
wire N_7;

or2i0 I26 ( .A(N_9), .B(one), .Q(N_8) );
and3i3 I23 ( .A(zero_r1), .B(zero), .C(holdoff), .Q(N_3) );
and2i2 I15 ( .A(zero), .B(one), .Q(nzeronone) );
mux2x2 I16 ( .A(N_10), .B(N_3), .Q(N_1), .S(flag_on) );
mux2x2 I17 ( .A(N_8), .B(N_7), .Q(N_4), .S(almost_on) );
and2i0 I19 ( .A(rw), .B(almost_on), .Q(N_10) );
and2i0 I24 ( .A(nzeronone), .B(nzeronone_r1), .Q(N_7) );
and2i0 I20 ( .A(rw), .B(two), .Q(N_9) );
dffpc I21 ( .CLK(clk), .CLR(reset), .D(N_1), .PRE(set), .Q(flag_on) );
dffpc I22 ( .CLK(clk), .CLR(reset), .D(N_4), .PRE(set), .Q(almost_on) );
dff I25 ( .CLK(clk), .D(nzeronone), .Q(nzeronone_r1) );
dff I13 ( .CLK(clk), .D(zero), .Q(zero_r1) );

endmodule // afifoflg

`endif

`ifdef dffpa
`else
`define dffpa
module dffpa( CLK , D, S, Q );
input CLK, D;
output Q;
input S;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
wire N_3;
supply0 GND;

frag_f I_3 ( .F1(VCC), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_a I_2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_q I_1 ( .QC(CLK), .QD(N_3), .QR(GND), .QS(S), .QZ(Q) );
frag_m QL1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(D),
          .E2(GND), .NS(N_1), .OS(N_2), .OZ(N_3) );

endmodule // dffpa

`endif

`ifdef ecomp5
`else
`define ecomp5
module ecomp5( A , B, EQ );
 input [4:0] A;
 input [4:0] B;
output EQ;
wire N_5;
wire N_1;
wire N_4;

and3i1 I_11 ( .A(N_1), .B(N_4), .C(N_5), .Q(EQ) );
xor2i0 I_12 ( .A(A[4]), .B(B[4]), .Q(N_5) );
ecompa I_9 ( .A({ A[3:2] }), .B({ B[3:2] }), .EQ2(N_4) );
ecompa I_10 ( .A({ A[1:0] }), .B({ B[1:0] }), .EQ2(N_1) );

endmodule // ecomp5

`endif

`ifdef hsckmux
`else
`define hsckmux
module hsckmux( IC , IS, IZ );
input IC, IS;
output IZ;
parameter ql_frag = 1;
 assign #1 IZ = IS ? IC : 1'b0;

endmodule // hsckmux

`endif

`ifdef ckcell_25um
`else
`define ckcell_25um
module ckcell_25um( IP , IC );
output IC;
input IP;
parameter ql_frag = 1;
 assign #1 IC = IP;

endmodule // ckcell_25um

`endif

`ifdef frag_q
`else
`define frag_q
module frag_q( QC , QD, QR, QS, QZ );
input QC, QD, QR, QS;
output QZ;
parameter ql_frag = 1;
 reg QZ;
`ifdef synthesis
 always @ (posedge QC or posedge QR or posedge QS) 
     if (QR)
        #1 QZ = 1'b0;
     else if (QS)
        #1 QZ = 1'b1;
     else #1 QZ = QD;
`else
  always @ (QR or QS) begin
      if (QR)
         #1 assign QZ = 1'b0;
      else if (QS)
         #1 assign QZ = 1'b1;
      else
         #1 deassign QZ;
  end
  always @ (posedge QC)
         QZ = #1 QD;
  initial begin
    #1;
    if (QR)
         #1 assign QZ = 1'b0;
    else if (QS)
         #1 assign QZ = 1'b1;
  end
 `endif

endmodule // frag_q

`endif

`ifdef and3i3
`else
`define and3i3
module and3i3( A , B, C, Q );
input A, B, C;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;

frag_a QL1 ( .A1(VCC), .A2(A), .A3(VCC), .A4(B), .A5(VCC), .A6(C), .AZ(Q) );

endmodule // and3i3

`endif

`ifdef and2i2
`else
`define and2i2
module and2i2( A , B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(A), .A5(VCC), .A6(B), .AZ(Q) );

endmodule // and2i2

`endif

`ifdef mux2x2
`else
`define mux2x2
module mux2x2( A , B, S, Q );
input A, B;
output Q;
input S;
parameter ql_gate = `LOGIC;
wire N_1;
supply1 VCC;
supply0 GND;
wire N_2;

frag_f I_2 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(A), .D2(GND), .E1(VCC),
          .E2(B), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // mux2x2

`endif

`ifdef dffpc
`else
`define dffpc
module dffpc( CLK , CLR, D, PRE, Q );
input CLK, CLR, D, PRE;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
wire N_3;
supply0 GND;

frag_f I_3 ( .F1(VCC), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_a I_2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_q I_1 ( .QC(CLK), .QD(N_3), .QR(CLR), .QS(PRE), .QZ(Q) );
frag_m QL1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(D),
          .E2(GND), .NS(N_1), .OS(N_2), .OZ(N_3) );

endmodule // dffpc

`endif

`ifdef xor2i0
`else
`define xor2i0
module xor2i0( A , B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
supply0 GND;
supply1 VCC;
wire N_2;

frag_a I_2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(B), .D2(GND), .E1(VCC),
          .E2(B), .NS(N_2), .NZ(Q), .OS(N_1) );
frag_f QL1 ( .F1(A), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_2) );

endmodule // xor2i0

`endif

`ifdef ecompa
`else
`define ecompa
module ecompa( A , B, EQ2 );
 input [1:0] A;
 input [1:0] B;
output EQ2;
supply1 vcc;
supply0 gnd;

logic2 I_2 ( .A1(vcc), .A2(B[0]), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd), .B1(vcc),
          .B2(gnd), .C1(gnd), .C2(gnd), .D1(gnd), .D2(gnd), .E1(gnd), .E2(gnd),
          .F1(vcc), .F2(B[1]), .F3(vcc), .F4(gnd), .F5(vcc), .F6(gnd), .MP(A[1]),
          .MS(B[1]), .NP(A[1]), .NS(B[1]), .OP(A[0]), .OS(B[0]), .OZ(EQ2),
          .QC(gnd), .QR(gnd), .QS(vcc) );

endmodule // ecompa

`endif

`ifdef logic2
`else
`define logic2
module logic2( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1, F2,
               F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, QC, QR, QS, AZ, FZ, NZ,
               OZ, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input QC, QR, QS;
output QZ;
parameter ql_gate = `LOGIC;

lcell2 I_2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ), .B1(B1),
          .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1), .E2(E2), .F1(F1),
          .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6), .FZ(FZ), .MP(MP), .MS(MS),
          .NP(NP), .NS(NS), .NZ(NZ), .OP(OP), .OS(OS), .OZ(OZ), .QC(QC), .QR(QR),
          .QS(QS), .QZ(QZ) );

endmodule // logic2

`endif

`ifdef lcell2
`else
`define lcell2
module lcell2( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1, F2,
               F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, QC, QR, QS, AZ, FZ, NZ,
               OZ, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input QC, QR, QS;
output QZ;
parameter ql_frag = 1;
 wire TOPMUX_Z, MIDMUX_Z, BOTMUX_Z; 
 wire MZ; 
 reg QZ; 
 
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6; 
 assign #1 TOPMUX_Z = OP ? AZ : OS;  
 assign #1 MZ = MIDMUX_Z ? (C1 & ~C2):(B1 & ~B2); 
 assign #1 MIDMUX_Z = MP ? FZ : MS;  
 assign #1 NZ = BOTMUX_Z ? (E1 & ~E2):(D1 & ~D2); 
 assign #1 BOTMUX_Z = NP ? FZ : NS;  
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6; 
 assign #1 OZ = TOPMUX_Z ? NZ : MZ;  
`ifdef synthesis 
 always @ (posedge QC or posedge QR or posedge QS)  
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
     else #1 QZ = OZ; 
`else 
  always @ (posedge QC) 
      if (~QR && ~QS) 
         #1 QZ = OZ; 
  always @ (QR or QS) 
      if (QR) 
         #1 QZ = 1'b0; 
      else if (QS) 
         #1 QZ = 1'b1; 
 `endif 

endmodule // lcell2

`endif