cardbus_5632.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

wire [4:0] Raddr1;
wire plus2;
wire plus1;
wire zero;
wire minus1;
wire minus2;
supply0 gnd;
wire N_2;
wire N_3;
wire N_4;
wire N_9;
wire N_10;
wire N_11;

r128x32_25um I137 ( .ra({ gnd,gnd,Raddr1[4:0] }), .rclk(rclk),
                 .rd({ dout[31:0] }), .re(N_11),
                 .wa({ gnd,gnd,Waddr0[4:0] }), .wclk(wclk),
                 .wd({ din[31:0] }), .we(N_4) );
afifoflg I135 ( .almost_on(almostfull), .clk(wclk), .flag_on(full),
             .holdoff(gnd), .one(minus1), .reset(wrst), .rw(push), .set(gnd),
             .two(minus2), .zero(zero) );
afifoflg I136 ( .almost_on(almostempty), .clk(rclk), .flag_on(empty),
             .holdoff(N_9), .one(plus1), .reset(gnd), .rw(pop), .set(rrst),
             .two(plus2), .zero(zero) );
dffpa I_120 ( .CLK(rclk), .D(gnd), .Q(N_9), .S(rrst) );
gcnte5_0 I_115 ( .CLK(wclk), .CLR(wrst), .EN(N_4), .Q({ Waddr0[4:0] }) );
rgec5_1r I_74 ( .CLK(rclk), .CLR(rrst), .D({ Raddr2[4:0] }), .EN(N_11),
             .Q({ Raddr1[4:0] }) );
rgec5_2 I_77 ( .CLK(wclk), .CLR(wrst), .D({ Waddr3[4:0] }), .EN(N_3),
            .Q({ Waddr2[4:0] }) );
gcnte5_2 I_78 ( .CLK(rclk), .CLR(rrst), .EN(N_2), .Q({ Raddr2[4:0] }) );
gcnte5_3 I_79 ( .CLK(wclk), .CLR(wrst), .EN(N_3), .Q({ Waddr3[4:0] }) );
or2i0 I_128 ( .A(N_10), .B(N_9), .Q(N_2) );
or2i0 I_45 ( .A(N_10), .B(N_9), .Q(N_11) );
and2i1 I_84 ( .A(push), .B(full), .Q(N_3) );
and2i1 I_50 ( .A(push), .B(full), .Q(N_4) );
and2i1 I_69 ( .A(pop), .B(empty), .Q(N_10) );
ecomp5 I_26 ( .A({ Waddr0[4:0] }), .B({ Raddr2[4:0] }), .EQ(plus2) );
ecomp5 I_19 ( .A({ Waddr0[4:0] }), .B({ Raddr1[4:0] }), .EQ(plus1) );
ecomp5 I_85 ( .A({ Waddr2[4:0] }), .B({ Raddr1[4:0] }), .EQ(minus1) );
ecomp5 I_18 ( .A({ Waddr3[4:0] }), .B({ Raddr1[4:0] }), .EQ(minus2) );
ecomp5 I_17 ( .A({ Waddr2[4:0] }), .B({ Raddr2[4:0] }), .EQ(zero) );

endmodule // f32a32_25um

`endif

`ifdef tripad_25um
`else
`define tripad_25um
module tripad_25um( A , EN, P );
input A, EN;
output P;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(EN), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // tripad_25um

`endif

`ifdef gclkbuff_25um
`else
`define gclkbuff_25um
module gclkbuff_25um( A , Z );
input A;
output Z;
parameter ql_gate = `HSCKMUX;
supply1 vcc;

hsckmux I1 ( .IC(A), .IS(vcc), .IZ(Z) );

endmodule // gclkbuff_25um

`endif

`ifdef bipadiff_25um
`else
`define bipadiff_25um
module bipadiff_25um( A2 , EN, FFCLK, FFCLR, FFEN, FFQ, Q, P );
input A2, EN, FFCLK, FFCLR, FFEN;
output FFQ;
inout P;
output Q;
parameter ql_gate = `BIDIR;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(FFCLK), .IQE(FFEN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(A2), .OSEL(vcc) );

endmodule // bipadiff_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P;
output Q;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef inpadff_25um
`else
`define inpadff_25um
module inpadff_25um( FFCLK , FFCLR, FFEN, P, FFQ, Q );
input FFCLK, FFCLR, FFEN;
output FFQ;
input P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(FFCLK), .IQE(FFEN),
           .IQQ(FFQ), .IQR(FFCLR), .IZ(Q), .OQI(gnd), .OSEL(vcc) );

endmodule // inpadff_25um

`endif

`ifdef and3i2
`else
`define and3i2
module and3i2( A , B, C, Q );
input A, B, C;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(VCC), .A4(B), .A5(VCC), .A6(C), .AZ(Q) );

endmodule // and3i2

`endif

`ifdef dff
`else
`define dff
module dff( CLK , D, Q );
input CLK, D;
output Q;
parameter ql_gate = `LOGIC;
supply0 GND;
wire N_1;
supply1 VCC;
wire N_2;
wire N_3;

frag_m I_3 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(D),
          .E2(GND), .NS(N_2), .OS(N_3), .OZ(N_1) );
frag_q I_2 ( .QC(CLK), .QD(N_1), .QR(GND), .QS(GND), .QZ(Q) );
frag_a I_1 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_3) );
frag_f QL1 ( .F1(VCC), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_2) );

endmodule // dff

`endif

`ifdef and4i3
`else
`define and4i3
module and4i3( A , B, C, D, Q );
input A, B, C, D;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;

frag_a QL1 ( .A1(A), .A2(D), .A3(VCC), .A4(B), .A5(VCC), .A6(C), .AZ(Q) );

endmodule // and4i3

`endif

`ifdef dffe
`else
`define dffe
module dffe( CLK , D, EN, Q );
input CLK, D, EN;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
wire N_3;
supply1 VCC;
supply0 GND;

frag_a I_3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_1) );
frag_m I_2 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(Q), .D2(GND), .E1(D),
          .E2(GND), .NS(N_3), .OS(N_1), .OZ(N_2) );
frag_q I_1 ( .QC(CLK), .QD(N_2), .QR(GND), .QS(GND), .QZ(Q) );
frag_f QL1 ( .F1(EN), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_3) );

endmodule // dffe

`endif

`ifdef and3i1
`else
`define and3i1
module and3i1( A , B, C, Q );
input A, B, C;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(B), .A4(GND), .A5(VCC), .A6(C), .AZ(Q) );

endmodule // and3i1

`endif

`ifdef or3i0
`else
`define or3i0
module or3i0( A , B, C, Q );
input A, B, C;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
supply0 GND;
wire N_2;
supply1 VCC;

frag_f I_2 ( .F1(VCC), .F2(A), .F3(VCC), .F4(B), .F5(VCC), .F6(C), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(GND),
          .E2(VCC), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // or3i0

`endif

`ifdef and2i1
`else
`define and2i1
module and2i1( A , B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(B), .AZ(Q) );

endmodule // and2i1

`endif

`ifdef and2i0
`else
`define and2i0
module and2i0( A , B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(B), .A4(GND), .A5(VCC), .A6(GND), .AZ(Q) );

endmodule // and2i0

`endif

`ifdef or2i0
`else
`define or2i0
module or2i0( A , B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
supply0 GND;
wire N_2;
supply1 VCC;

frag_f I_2 ( .F1(VCC), .F2(A), .F3(VCC), .F4(B), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(GND),
          .E2(VCC), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // or2i0

`endif

`ifdef mux2x0
`else
`define mux2x0
module mux2x0( A , B, S, Q );
input A, B;
output Q;
input S;
parameter ql_gate = `LOGIC;
wire N_1;
supply1 VCC;
supply0 GND;
wire N_2;

frag_f I_2 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(A), .D2(GND), .E1(B),
          .E2(GND), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // mux2x0

`endif

`ifdef dffp
`else
`define dffp
module dffp( CLK , D, PRE, Q );
input CLK, D, PRE;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
wire N_3;
supply0 GND;

frag_f I_3 ( .F1(VCC), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_a I_2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_q I_1 ( .QC(CLK), .QD(N_3), .QR(GND), .QS(PRE), .QZ(Q) );
frag_m QL1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(D),
          .E2(GND), .NS(N_1), .OS(N_2), .OZ(N_3) );

endmodule // dffp

`endif

`ifdef inv
`else
`define inv
module inv( A , Q );
input A;
output Q;
parameter ql_gate = `LOGIC;
supply0 GND;
supply1 VCC;

frag_a QL1 ( .A1(VCC), .A2(A), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(Q) );

endmodule // inv

`endif

`ifdef frag_a
`else
`define frag_a
module frag_a( A1 , A2, A3, A4, A5, A6, AZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
parameter ql_frag = 1;
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6;

endmodule // frag_a

`endif

`ifdef frag_f
`else
`define frag_f
module frag_f( F1 , F2, F3, F4, F5, F6, FZ );
input F1, F2, F3, F4, F5, F6;
output FZ;
parameter ql_frag = 1;
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6;

endmodule // frag_f

`endif