📄 cardbus_5632.v
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inpad_25um \CIS_data[13] ( .P(pad_CIS_data[13]), .Q(CIS_data[13]) );
inpad_25um \CIS_data[12] ( .P(pad_CIS_data[12]), .Q(CIS_data[12]) );
inpad_25um \CIS_data[11] ( .P(pad_CIS_data[11]), .Q(CIS_data[11]) );
inpad_25um \CIS_data[10] ( .P(pad_CIS_data[10]), .Q(CIS_data[10]) );
inpad_25um \CIS_data[9] ( .P(pad_CIS_data[9]), .Q(CIS_data[9]) );
inpad_25um \CIS_data[8] ( .P(pad_CIS_data[8]), .Q(CIS_data[8]) );
inpad_25um \CIS_data[7] ( .P(pad_CIS_data[7]), .Q(CIS_data[7]) );
inpad_25um \CIS_data[6] ( .P(pad_CIS_data[6]), .Q(CIS_data[6]) );
inpad_25um \CIS_data[5] ( .P(pad_CIS_data[5]), .Q(CIS_data[5]) );
inpad_25um \CIS_data[4] ( .P(pad_CIS_data[4]), .Q(CIS_data[4]) );
inpad_25um \CIS_data[3] ( .P(pad_CIS_data[3]), .Q(CIS_data[3]) );
inpad_25um \CIS_data[2] ( .P(pad_CIS_data[2]), .Q(CIS_data[2]) );
inpad_25um \CIS_data[1] ( .P(pad_CIS_data[1]), .Q(CIS_data[1]) );
inpad_25um \CIS_data[0] ( .P(pad_CIS_data[0]), .Q(CIS_data[0]) );
bipad_25um I229 ( .A(CCLKRUN_n_out), .EN(CCLKRUN_n_oe), .P(pad_CCLKRUN_n),
.Q(CCLKRUN_n_in) );
cardbus_wrapper I222 ( .addr_phase(Usr_Adr_Valid), .BAM_in(BAM_in),
.BAR_match(CardBus_BAR), .bvd_ps({ bvd_ps[2:1] }),
.CAUDIO(CAUDIO), .CBLOCK_n(CBLOCK_n),
.CCLKRUN_n_in(CCLKRUN_n_in),
.CCLKRUN_n_oe(CCLKRUN_n_oe),
.CCLKRUN_n_out(CCLKRUN_n_out), .CINT_n(CINT_n),
.clk(PCI_clock), .clk_resume(clk_resume),
.clk_stopped(clk_stopped), .CSTSCHG(CSTSCHG),
.cstschg_rdy(cstschg_rdy),
.cstschg_regs_in({ Usr_Addr_WrData[31:0] }),
.cstschg_regs_oe(RdData_MUX_sel),
.cstschg_regs_out({ cstschg_regs[31:0] }),
.framen_d1(PCI_FRAME_D1), .gwake_ps(gwake_ps),
.intr_ps(intr_ps), .locked(locked),
.owner_access(owner_access), .PWM_in(PWM_in),
.ready_ps(ready_ps), .reset(PCI_reset),
.user_addr({ ADR[9:0] }), .usr_read(Usr_Read),
.usr_write(Usr_Write), .wp_ps(wp_ps) );
f32a32_25um Rdbuff ( .almostempty(RdBuff_almost_empty),
.din({ RdBuff_mux[31:0] }), .dout({ RdBuff_out[31:0] }),
.empty(RdBuff_empty), .full(RdBuff_full), .pop(we_int),
.push(N_28), .rclk(local_clock), .rrst(loc_sync_reset),
.wclk(PCI_clock), .wrst(local_reset) );
f32a32_25um WrBuff ( .almostempty(WrBuff_almost_empty),
.almostfull(WrBuff_almost_full),
.din({ WrBuff_in[31:0] }),
.dout({ Mst_WrData_FIFO[31:0] }), .empty(WrBuff_empty),
.full(WrBuff_full), .pop(N_26), .push(re_dly),
.rclk(PCI_clock), .rrst(local_reset), .wclk(local_clock),
.wrst(loc_sync_reset) );
tripad_25um I170 ( .A(VCC), .EN(GND), .P(INTAN) );
gclkbuff_25um I187 ( .A(N_20), .Z(loc_sync_reset) );
gclkbuff_25um I188 ( .A(N_19), .Z(local_reset) );
gclkbuff_25um I215 ( .A(fpga_oe), .Z(N_23) );
bipadiff_25um \ladpads[31] ( .A2(RdBuff_out[31]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[31]), .P(lad[31]), .Q(WrD[31]) );
bipadiff_25um \ladpads[30] ( .A2(RdBuff_out[30]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[30]), .P(lad[30]), .Q(WrD[30]) );
bipadiff_25um \ladpads[29] ( .A2(RdBuff_out[29]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[29]), .P(lad[29]), .Q(WrD[29]) );
bipadiff_25um \ladpads[28] ( .A2(RdBuff_out[28]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[28]), .P(lad[28]), .Q(WrD[28]) );
bipadiff_25um \ladpads[27] ( .A2(RdBuff_out[27]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[27]), .P(lad[27]), .Q(WrD[27]) );
bipadiff_25um \ladpads[26] ( .A2(RdBuff_out[26]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[26]), .P(lad[26]), .Q(WrD[26]) );
bipadiff_25um \ladpads[25] ( .A2(RdBuff_out[25]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[25]), .P(lad[25]), .Q(WrD[25]) );
bipadiff_25um \ladpads[24] ( .A2(RdBuff_out[24]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[24]), .P(lad[24]), .Q(WrD[24]) );
bipadiff_25um \ladpads[23] ( .A2(RdBuff_out[23]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[23]), .P(lad[23]), .Q(WrD[23]) );
bipadiff_25um \ladpads[22] ( .A2(RdBuff_out[22]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[22]), .P(lad[22]), .Q(WrD[22]) );
bipadiff_25um \ladpads[21] ( .A2(RdBuff_out[21]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[21]), .P(lad[21]), .Q(WrD[21]) );
bipadiff_25um \ladpads[20] ( .A2(RdBuff_out[20]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[20]), .P(lad[20]), .Q(WrD[20]) );
bipadiff_25um \ladpads[19] ( .A2(RdBuff_out[19]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[19]), .P(lad[19]), .Q(WrD[19]) );
bipadiff_25um \ladpads[18] ( .A2(RdBuff_out[18]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[18]), .P(lad[18]), .Q(WrD[18]) );
bipadiff_25um \ladpads[17] ( .A2(RdBuff_out[17]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[17]), .P(lad[17]), .Q(WrD[17]) );
bipadiff_25um \ladpads[16] ( .A2(RdBuff_out[16]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[16]), .P(lad[16]), .Q(WrD[16]) );
bipadiff_25um \ladpads[15] ( .A2(RdBuff_out[15]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[15]), .P(lad[15]), .Q(WrD[15]) );
bipadiff_25um \ladpads[14] ( .A2(RdBuff_out[14]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[14]), .P(lad[14]), .Q(WrD[14]) );
bipadiff_25um \ladpads[13] ( .A2(RdBuff_out[13]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[13]), .P(lad[13]), .Q(WrD[13]) );
bipadiff_25um \ladpads[12] ( .A2(RdBuff_out[12]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[12]), .P(lad[12]), .Q(WrD[12]) );
bipadiff_25um \ladpads[11] ( .A2(RdBuff_out[11]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[11]), .P(lad[11]), .Q(WrD[11]) );
bipadiff_25um \ladpads[10] ( .A2(RdBuff_out[10]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[10]), .P(lad[10]), .Q(WrD[10]) );
bipadiff_25um \ladpads[9] ( .A2(RdBuff_out[9]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[9]), .P(lad[9]), .Q(WrD[9]) );
bipadiff_25um \ladpads[8] ( .A2(RdBuff_out[8]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[8]), .P(lad[8]), .Q(WrD[8]) );
bipadiff_25um \ladpads[7] ( .A2(RdBuff_out[7]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[7]), .P(lad[7]), .Q(WrD[7]) );
bipadiff_25um \ladpads[6] ( .A2(RdBuff_out[6]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[6]), .P(lad[6]), .Q(WrD[6]) );
bipadiff_25um \ladpads[5] ( .A2(RdBuff_out[5]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[5]), .P(lad[5]), .Q(WrD[5]) );
bipadiff_25um \ladpads[4] ( .A2(RdBuff_out[4]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[4]), .P(lad[4]), .Q(WrD[4]) );
bipadiff_25um \ladpads[3] ( .A2(RdBuff_out[3]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[3]), .P(lad[3]), .Q(WrD[3]) );
bipadiff_25um \ladpads[2] ( .A2(RdBuff_out[2]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[2]), .P(lad[2]), .Q(WrD[2]) );
bipadiff_25um \ladpads[1] ( .A2(RdBuff_out[1]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[1]), .P(lad[1]), .Q(WrD[1]) );
bipadiff_25um \ladpads[0] ( .A2(RdBuff_out[0]), .EN(N_23), .FFCLK(local_clock),
.FFCLR(loc_sync_reset), .FFEN(N_25),
.FFQ(WrBuff_in[0]), .P(lad[0]), .Q(WrD[0]) );
ckpad_25um I189 ( .P(lclk), .Q(local_clock) );
outpad_25um I241 ( .A(owner_access), .P(pad_owner_access) );
outpad_25um I242 ( .A(locked), .P(pad_locked) );
outpad_25um I243 ( .A(clk_stopped), .P(pad_clk_stopped) );
outpad_25um I230 ( .A(CAUDIO), .P(pad_CAUDIO) );
outpad_25um I231 ( .A(CSTSCHG), .P(pad_CSTSCHG) );
outpad_25um I232 ( .A(CINT_n), .P(pad_CINT_n) );
outpad_25um \CIS_ADR[9] ( .A(ADR[9]), .P(pad_CIS_ADR[9]) );
outpad_25um \CIS_ADR[8] ( .A(ADR[8]), .P(pad_CIS_ADR[8]) );
outpad_25um \CIS_ADR[7] ( .A(ADR[7]), .P(pad_CIS_ADR[7]) );
outpad_25um \CIS_ADR[6] ( .A(ADR[6]), .P(pad_CIS_ADR[6]) );
outpad_25um \CIS_ADR[5] ( .A(ADR[5]), .P(pad_CIS_ADR[5]) );
outpad_25um \CIS_ADR[4] ( .A(ADR[4]), .P(pad_CIS_ADR[4]) );
outpad_25um \CIS_ADR[3] ( .A(ADR[3]), .P(pad_CIS_ADR[3]) );
outpad_25um \CIS_ADR[2] ( .A(ADR[2]), .P(pad_CIS_ADR[2]) );
outpad_25um I217 ( .A(N_18), .P(mrs) );
outpad_25um \ledpads[7] ( .A(mxledoi[7]), .P(led[7]) );
outpad_25um \ledpads[6] ( .A(mxledoi[6]), .P(led[6]) );
outpad_25um \ledpads[5] ( .A(mxledoi[5]), .P(led[5]) );
outpad_25um \ledpads[4] ( .A(mxledoi[4]), .P(led[4]) );
outpad_25um \ledpads[3] ( .A(mxledoi[3]), .P(led[3]) );
outpad_25um \ledpads[2] ( .A(mxledoi[2]), .P(led[2]) );
outpad_25um \ledpads[1] ( .A(mxledoi[1]), .P(led[1]) );
outpad_25um \ledpads[0] ( .A(mxledoi[0]), .P(led[0]) );
outpad_25um I201 ( .A(N_31), .P(wen) );
outpad_25um I202 ( .A(N_32), .P(ren) );
outpad_25um I203 ( .A(fifo_oe_n), .P(oe) );
outpad_25um I204 ( .A(ldn), .P(ld) );
inpadff_25um I205 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(irn_in),
.P(ir_n) );
inpadff_25um I207 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(orn_in),
.P(or_n) );
inpadff_25um I208 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(paen_in),
.P(pae_n) );
inpadff_25um I209 ( .FFCLK(local_clock), .FFCLR(GND), .FFEN(VCC), .FFQ(pafn_in),
.P(paf_n) );
and3i2 I165 ( .A(WrBuff_fullN), .B(fpga_oe), .C(N_24), .Q(N_25) );
dff I166 ( .CLK(local_clock), .D(fpga_oe), .Q(N_24) );
and4i3 I159 ( .A(PCI_Cmd[0]), .B(PCI_Cmd[1]), .C(PCI_Cmd[2]), .D(PCI_Cmd[3]),
.Q(N_22) );
dffe I160 ( .CLK(PCI_clock), .D(N_22), .EN(Mst_Burst_Req), .Q(MstSC) );
and3i1 I157 ( .A(PCI_Cmd[0]), .B(Mst_WrData_Rdy), .C(Mst_Data_Sel), .Q(N_26) );
or3i0 I153 ( .A(N_29), .B(Mst_TTO_Det), .C(N_30), .Q(DMA_Error) );
and2i1 I154 ( .A(BEFIFO_pop), .B(BEFIFO_emptyn), .Q(N_30) );
and2i1 I158 ( .A(Mst_RdData_Valid), .B(Mst_Data_Sel), .Q(N_27) );
and2i0 I163 ( .A(Mst_WrData_Rdy), .B(Mst_BE_Sel), .Q(BEFIFO_pop) );
and2i0 I147 ( .A(N_28), .B(RdBuff_full), .Q(N_29) );
or2i0 I145 ( .A(Cfg_Stop), .B(Prog_Stop), .Q(Usr_Stop) );
or2i0 I161 ( .A(Usr_Write), .B(Cfg_Write), .Q(N_21) );
mux2x0 \Mst_WrData_Mux[31] ( .A(Mst_WrData_FIFO[31]), .B(Mst_WrData_Reg[31]),
.Q(Mst_WrData[31]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[30] ( .A(Mst_WrData_FIFO[30]), .B(Mst_WrData_Reg[30]),
.Q(Mst_WrData[30]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[29] ( .A(Mst_WrData_FIFO[29]), .B(Mst_WrData_Reg[29]),
.Q(Mst_WrData[29]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[28] ( .A(Mst_WrData_FIFO[28]), .B(Mst_WrData_Reg[28]),
.Q(Mst_WrData[28]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[27] ( .A(Mst_WrData_FIFO[27]), .B(Mst_WrData_Reg[27]),
.Q(Mst_WrData[27]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[26] ( .A(Mst_WrData_FIFO[26]), .B(Mst_WrData_Reg[26]),
.Q(Mst_WrData[26]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[25] ( .A(Mst_WrData_FIFO[25]), .B(Mst_WrData_Reg[25]),
.Q(Mst_WrData[25]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[24] ( .A(Mst_WrData_FIFO[24]), .B(Mst_WrData_Reg[24]),
.Q(Mst_WrData[24]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[23] ( .A(Mst_WrData_FIFO[23]), .B(Mst_WrData_Reg[23]),
.Q(Mst_WrData[23]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[22] ( .A(Mst_WrData_FIFO[22]), .B(Mst_WrData_Reg[22]),
.Q(Mst_WrData[22]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[21] ( .A(Mst_WrData_FIFO[21]), .B(Mst_WrData_Reg[21]),
.Q(Mst_WrData[21]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[20] ( .A(Mst_WrData_FIFO[20]), .B(Mst_WrData_Reg[20]),
.Q(Mst_WrData[20]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[19] ( .A(Mst_WrData_FIFO[19]), .B(Mst_WrData_Reg[19]),
.Q(Mst_WrData[19]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[18] ( .A(Mst_WrData_FIFO[18]), .B(Mst_WrData_Reg[18]),
.Q(Mst_WrData[18]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[17] ( .A(Mst_WrData_FIFO[17]), .B(Mst_WrData_Reg[17]),
.Q(Mst_WrData[17]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[16] ( .A(Mst_WrData_FIFO[16]), .B(Mst_WrData_Reg[16]),
.Q(Mst_WrData[16]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[15] ( .A(Mst_WrData_FIFO[15]), .B(Mst_WrData_Reg[15]),
.Q(Mst_WrData[15]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[14] ( .A(Mst_WrData_FIFO[14]), .B(Mst_WrData_Reg[14]),
.Q(Mst_WrData[14]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[13] ( .A(Mst_WrData_FIFO[13]), .B(Mst_WrData_Reg[13]),
.Q(Mst_WrData[13]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[12] ( .A(Mst_WrData_FIFO[12]), .B(Mst_WrData_Reg[12]),
.Q(Mst_WrData[12]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[11] ( .A(Mst_WrData_FIFO[11]), .B(Mst_WrData_Reg[11]),
.Q(Mst_WrData[11]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[10] ( .A(Mst_WrData_FIFO[10]), .B(Mst_WrData_Reg[10]),
.Q(Mst_WrData[10]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[9] ( .A(Mst_WrData_FIFO[9]), .B(Mst_WrData_Reg[9]),
.Q(Mst_WrData[9]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[8] ( .A(Mst_WrData_FIFO[8]), .B(Mst_WrData_Reg[8]),
.Q(Mst_WrData[8]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[7] ( .A(Mst_WrData_FIFO[7]), .B(Mst_WrData_Reg[7]),
.Q(Mst_WrData[7]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[6] ( .A(Mst_WrData_FIFO[6]), .B(Mst_WrData_Reg[6]),
.Q(Mst_WrData[6]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[5] ( .A(Mst_WrData_FIFO[5]), .B(Mst_WrData_Reg[5]),
.Q(Mst_WrData[5]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[4] ( .A(Mst_WrData_FIFO[4]), .B(Mst_WrData_Reg[4]),
.Q(Mst_WrData[4]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[3] ( .A(Mst_WrData_FIFO[3]), .B(Mst_WrData_Reg[3]),
.Q(Mst_WrData[3]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[2] ( .A(Mst_WrData_FIFO[2]), .B(Mst_WrData_Reg[2]),
.Q(Mst_WrData[2]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[1] ( .A(Mst_WrData_FIFO[1]), .B(Mst_WrData_Reg[1]),
.Q(Mst_WrData[1]), .S(Mst_Data_Sel) );
mux2x0 \Mst_WrData_Mux[0] ( .A(Mst_WrData_FIFO[0]), .B(Mst_WrData_Reg[0]),
.Q(Mst_WrData[0]), .S(Mst_Data_Sel) );
mux2x0 \mxled[7] ( .A(WrBuff_full), .B(ledout[7]), .Q(mxledo[7]), .S(ledcntrl) );
mux2x0 \mxled[6] ( .A(WrBuff_empty), .B(ledout[6]), .Q(mxledo[6]), .S(ledcntrl) );
mux2x0 \mxled[5] ( .A(RdBuff_full), .B(ledout[5]), .Q(mxledo[5]), .S(ledcntrl) );
mux2x0 \mxled[4] ( .A(RdBuff_empty), .B(ledout[4]), .Q(mxledo[4]), .S(ledcntrl) );
mux2x0 \mxled[3] ( .A(orn_in), .B(ledout[3]), .Q(mxledo[3]), .S(ledcntrl) );
mux2x0 \mxled[2] ( .A(paen_in), .B(ledout[2]), .Q(mxledo[2]), .S(ledcntrl) );
mux2x0 \mxled[1] ( .A(pafn_in), .B(ledout[1]), .Q(mxledo[1]), .S(ledcntrl) );
mux2x0 \mxled[0] ( .A(irn_in), .B(ledout[0]), .Q(mxledo[0]), .S(ledcntrl) );
dmaregrd I_137 ( .adr({ ADR[9:2] }), .CBE({ Usr_CBE[3:0] }), .clk(PCI_clock),
.clkspd({ s1en,s0en,s1s0 }), .clr(PCI_reset),
.dataout({ Usr_RdDataIn[31:0] }), .DMARdEn(DMARdEn),
.DMAWrEn(DMAWrEn), .IncrAddr(Usr_Adr_Inc),
.led({ ledout[7:0] }), .ledcntrl(ledcntrl),
.LoadAddr(Usr_Adr_Valid),
.PCI_data({ Usr_Addr_WrData[31:0] }), .PCI_Wr(N_21),
.Usr_Rdy(Mem_Rdy), .Usr_Stop(Prog_Stop) );
fifocont I_134 ( .clk(local_clock), .clr(loc_sync_reset), .fpga_oe(fpga_oe),
.idt_fifo_ae_n(paen_in), .idt_fifo_af_n(pafn_in),
.idt_fifo_empty(orn_in), .idt_fifo_full(irn_in),
.idt_fifo_oe_n(fifo_oe_n), .ldn(ldn),
.rbuff_ae(RdBuff_almost_empty), .rbuff_empty(RdBuff_empty),
.re(re_out), .re_dly(re_dly), .wbuff_af(WrBuff_almost_full),
.wbuff_full(WrBuff_full), .we(we_out), .we_int(we_int) );
dffp I_124 ( .CLK(local_clock), .D(N_19), .PRE(PCI_reset), .Q(N_20) );
dffp I149 ( .CLK(PCI_clock), .D(RdBuff_empty), .PRE(local_reset),
.Q(RdBuff_empty_sync) );
initflgs I_114 ( .clk(PCI_clock), .clr(local_reset),
.datain({ Usr_Addr_WrData[31:0] }),
.dataout({ RdBuff_mux[31:0] }), .push(N_28), .pushin(N_27) );
inv I218 ( .A(N_20), .Q(N_18) );
inv I_129 ( .A(LocalEn), .Q(N_19) );
inv \ledinv[7] ( .A(mxledo[7]), .Q(mxledoi[7]) );
inv \ledinv[6] ( .A(mxledo[6]), .Q(mxledoi[6]) );
inv \ledinv[5] ( .A(mxledo[5]), .Q(mxledoi[5]) );
inv \ledinv[4] ( .A(mxledo[4]), .Q(mxledoi[4]) );
inv \ledinv[3] ( .A(mxledo[3]), .Q(mxledoi[3]) );
inv \ledinv[2] ( .A(mxledo[2]), .Q(mxledoi[2]) );
inv \ledinv[1] ( .A(mxledo[1]), .Q(mxledoi[1]) );
inv \ledinv[0] ( .A(mxledo[0]), .Q(mxledoi[0]) );
inv I146 ( .A(WrBuff_full), .Q(WrBuff_fullN) );
inv I_80 ( .A(RdBuff_full), .Q(RdBuff_fullN) );
inv I_81 ( .A(WrBuff_empty), .Q(WrBuff_emptyN) );
inv I212 ( .A(re_out), .Q(N_32) );
inv I213 ( .A(we_out), .Q(N_31) );
dmacntrl DMA ( .BEfifo(BEfifo), .BusMstEn(Cfg_CmdReg[2]), .DMARdEn(DMARdEn),
.DMAWrEn(DMAWrEn), .IncrAddr(Usr_Adr_Inc),
.LastWr(WrBuff_almost_empty), .LocalEn(LocalEn),
.Mst_BE({ Mst_BE[3:0] }), .Mst_BE_FIFO({ Mst_BE_FIFO[3:0] }),
.Mst_BE_Sel(Mst_BE_Sel), .Mst_Burst_Req(Mst_Burst_Req),
.Mst_Data_Sel(Mst_Data_Sel), .Mst_LatCntEn(Mst_LatCntEn),
.Mst_One_Read(Mst_One_Read), .Mst_Rd_Term_Sel(Mst_Rd_Term_Sel),
.Mst_RdAd({ Mst_RdAd[31:0] }),
.Mst_RdBurst_Done(Mst_RdBurst_Done),
.Mst_RdData_Valid(Mst_RdData_Valid),
.Mst_Tabort_Det(Mst_Tabort_Det), .Mst_TTO_Det(DMA_Error),
.Mst_Two_Reads(Mst_Two_Reads), .Mst_WrAd({ Mst_WrAd[31:0] }),
.Mst_WrBurst_Done(Mst_WrBurst_Done),
.Mst_WrData_Rdy(Mst_WrData_Rdy),
.Mst_WrData_Valid(Mst_WrData_Valid), .Mst_Xfer_D1(Mst_Xfer_D1),
.MstRdAd_Sel(Usr_MstRdAd_Sel), .MstWrAd_Sel(Usr_MstWrAd_Sel),
.PCI_clk(PCI_clock), .PCI_Cmd({ PCI_Cmd[3:0] }),
.PCI_reset(PCI_reset), .RdRdy(RdBuff_empty_sync),
.Usr_Ad({ ADR[9:2] }), .Usr_CBE({ Usr_CBE[3:0] }),
.Usr_RdData({ mem_RdData[31:0] }),
.Usr_RdDataIn({ Usr_RdDataIn[31:0] }),
.Usr_WrData({ Usr_Addr_WrData[31:0] }), .Usr_Write(Usr_Write),
.WD_Reg({ Mst_WrData_Reg[31:0] }), .WrRdy(WrBuff_emptyN) );
endmodule // cardbus_5632
`ifdef mux4x0
`else
`define mux4x0
module mux4x0( A , B, C, D, S0, S1, Q );
input A, B, C, D;
output Q;
input S0, S1;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
supply0 GND;
frag_a I_2 ( .A1(S1), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_f I_1 ( .F1(S0), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m QL3 ( .B1(A), .B2(GND), .C1(B), .C2(GND), .D1(C), .D2(GND), .E1(D), .E2(GND),
.NS(N_1), .OS(N_2), .OZ(Q) );
endmodule // mux4x0
`endif
`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;
eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
.IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );
endmodule // inpad_25um
`endif
`ifdef bipad_25um
`else
`define bipad_25um
module bipad_25um( A , EN, Q, P );
input A, EN;
inout P;
output Q;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;
eio_cell I2 ( .EQE(vcc), .ESEL(vcc), .IE(EN), .IP(P), .IQC(gnd), .IQE(gnd),
.IQR(gnd), .IZ(Q), .OQI(A), .OSEL(vcc) );
endmodule // bipad_25um
`endif
`ifdef f32a32_25um
`else
`define f32a32_25um
module f32a32_25um( din , pop, push, rclk, rrst, wclk, wrst, almostempty,
almostfull, dout, empty, full );
output almostempty, almostfull;
input [31:0] din;
output [31:0] dout;
output empty, full;
input pop, push, rclk, rrst, wclk, wrst;
wire [4:0] Raddr2;
wire [4:0] Waddr2;
wire [4:0] Waddr3;
wire [4:0] Waddr0;
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