cardbus_5632aldec.do

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

####################################################################
# File name : cardbus_5632aldec.do
# Active HDL macro script 
# To perform pre layout simulation
####################################################################

#set curpath c:\pasic\design\reference\pci5632_280\verilog
set curpath d:\project\CardBus\Source\verilog

#set primitivepath C:\pasic\spde\data\Ql5632-33\pci32_25um
set primitivepath d:\pasic\spde\data\ql5632-33\pci32_25um

set design_name cardbus_5632
set adf_file_name cardbus_5632.adf 

createdesign $design_name $curpath
opendesign $adf_file_name

alib work
set worklib work

addfile -c -txt $curpath/bus_chk.mem

addfile -verilog $primitivepath/V1_2/pci3233_25um.v
alog $primitivepath/V1_2/pci3233_25um.v

addfile -verilog $curpath/cardbus_5632.v
alog $curpath/cardbus_5632.v

addfile -verilog $curpath/cardbus_5632.tf
alog $curpath/cardbus_5632.tf

vsim -t 100ps cardbus_5632 t

view wave

wave /t/PERRN
wave /t/SERRN
wave /t/PAR
wave /t/REQN
wave /t/GNTN
wave /t/RSTN
wave /t/CLK
wave /t/IDSEL
wave -literal -hex /t/AD
wave -literal -hex /t/CBEN
wave /t/FRAMEN
wave /t/IRDYN
wave /t/DEVSELN
wave /t/TRDYN
wave /t/STOPN

run -all
#write mem cardbus_5632aldec.log
#endsim