cardbus_5632.qdf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

   term QR port QR end
   term QS port QS end
   term AZ port AZ end
   term FZ port FZ end
   term NZ port NZ end
   term OZ port OZ end
   term QZ port QZ end
   term VCC end
   term GND end
 end
 gate xor2i0 cell LOGIC
   term A port F1 end
   term B port E2 port D1 end
   term Q port NZ end
   term VCC port A3 port A5 port B1 port C1 port E1 port F3 port F5 port A1 end
   term GND port A4 port A6 port B2 port C2 port D2 port F2 port F4 port F6 port A2 end
 end
 gate dffpa cell LOGIC
   term CLK port QC end
   term D port E1 end
   term S port QS end
   term Q port QZ end
   term VCC port F3 port F5 port A1 port A3 port A5 port B1 port C1 port D1 port F1 end
   term GND port F4 port F6 port A2 port A4 port A6 port QR port B2 port C2 port D2 port E2 port F2 end
 end
 gate Q_DECX cell LOGIC
   term A port E2 port D1 end
   term E1 port F2 end
   term E2 port F4 end
   term E3 port F6 end
   term NE4 port F1 end
   term NE5 port F3 end
   term S port NZ end
   term VCC port F5 port E1 end
   term GND port D2 port C2 port C1 port B2 port B1 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate Q_INCX cell LOGIC
   term A port E2 port D1 end
   term E1 port F1 end
   term E2 port F3 end
   term E3 port F5 end
   term NE4 port F2 end
   term NE5 port F4 end
   term S port NZ end
   term VCC port E1 end
   term GND port F6 port D2 port C2 port C1 port B2 port B1 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate Q_AND2 cell LOGIC
   term A port A1 end
   term B port A3 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A6 port A4 port A2 end
 end
 gate Q_INCSKIP cell LOGIC
   term CI port E1 end
   term A0 port F1 end
   term A1 port F3 end
   term A2 port F5 end
   term CO port NZ end
   term VCC port C1 port B1 end
   term GND port F6 port F4 port F2 port E2 port D2 port D1 port C2 port B2 port A6 port A5 port A4 port A3 port A2 port A1 end
 end
 gate Q_INCSKIP2 cell LOGIC
   term CI port E1 end
   term A0 port F1 end
   term A1 port F3 end
   term A2 port F5 end
   term CO3 port NZ end
   term A3 port A1 end
   term A4 port A3 end
   term A5 port A5 end
   term CO6 port OZ end
   term VCC end
   term GND port F6 port F4 port F2 port E2 port D2 port D1 port C2 port C1 port B2 port B1 port A6 port A4 port A2 end
 end
 gate dnfxbit cell LOGIC
   term CLK port QC end
   term CLR port QR end
   term D port E1 port D1 end
   term ENG port F5 end
   term ENP port F1 end
   term ENT port F3 end
   term LOAD port A5 end
   term Q port QZ port C2 port B1 end
   term Q0 port F2 end
   term Q1 port F4 end
   term Q2 port F6 end
   term VCC port A1 port A3 port C1 end
   term GND port B2 port D2 port E2 port A2 port A4 port A6 port QS end
 end
 gate and5i4 cell LOGIC
   term A port F1 end
   term B port E2 end
   term C port F2 end
   term D port F4 end
   term E port F6 end
   term Q port NZ end
   term VCC port F5 port B1 port C1 port D2 port E1 port A1 port A3 port A5 port F3 end
   term GND port C2 port D1 port A2 port A4 port A6 port B2 end
 end
 gate inv cell LOGIC
   term A port A2 end
   term Q port AZ end
   term VCC port A3 port A5 port A1 end
   term GND port A6 port A4 end
 end
 gate dffp cell LOGIC
   term CLK port QC end
   term D port E1 end
   term PRE port QS end
   term Q port QZ end
   term VCC port F3 port F5 port A1 port A3 port A5 port B1 port C1 port D1 port F1 end
   term GND port F4 port F6 port A2 port A4 port A6 port QR port B2 port C2 port D2 port E2 port F2 end
 end
 gate Q_MUX2X0 cell LOGIC
   term A port D1 end
   term B port E1 end
   term S port F1 end
   term Q port NZ end
   term VCC port A5 port A3 port A1 port C1 port B1 port F5 port F3 end
   term GND port A6 port A4 port A2 port E2 port D2 port C2 port B2 port F6 port F4 port F2 end
 end
 gate or2i0 cell LOGIC
   term A port F2 end
   term B port F4 end
   term Q port NZ end
   term VCC port F3 port F5 port B1 port C1 port D1 port E2 port A1 port A3 port A5 port F1 end
   term GND port B2 port C2 port D2 port E1 port A2 port A4 port A6 port F6 end
 end
 gate Q_AND2I0 cell LOGIC
   term A port A1 end
   term B port A3 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A6 port A4 port A2 end
 end
 gate and2i1 cell LOGIC
   term A port A1 end
   term B port A6 end
   term Q port AZ end
   term VCC port A5 port A3 end
   term GND port A4 port A2 end
 end
 gate or3i0 cell LOGIC
   term A port F2 end
   term B port F4 end
   term C port F6 end
   term Q port NZ end
   term VCC port F3 port F5 port B1 port C1 port D1 port E2 port A1 port A3 port A5 port F1 end
   term GND port C2 port D2 port E1 port A2 port A4 port A6 port B2 end
 end
 gate and3i1 cell LOGIC
   term A port A1 end
   term B port A3 end
   term C port A6 end
   term Q port AZ end
   term VCC port A5 end
   term GND port A4 port A2 end
 end
 gate dffe cell LOGIC
   term CLK port QC end
   term D port E1 end
   term EN port F1 end
   term Q port QZ port D1 end
   term VCC port A3 port A5 port B1 port C1 port F3 port F5 port A1 end
   term GND port A4 port A6 port B2 port C2 port D2 port E2 port QR port QS port F2 port F4 port F6 port A2 end
 end
 gate and4i3 cell LOGIC
   term A port A1 end
   term B port A4 end
   term C port A6 end
   term D port A2 end
   term Q port AZ end
   term VCC port A5 port A3 end
 end
 gate dff cell LOGIC
   term CLK port QC end
   term D port E1 end
   term Q port QZ end
   term VCC port C1 port D1 port A1 port A3 port A5 port F1 port F3 port F5 port B1 end
   term GND port C2 port D2 port E2 port QR port QS port A2 port A4 port A6 port F2 port F4 port F6 port B2 end
 end
 gate and3i2 cell LOGIC
   term A port A1 end
   term B port A4 end
   term C port A6 end
   term Q port AZ end
   term VCC port A5 port A3 end
   term GND port A2 end
 end
 gate inpadff_25um cell BIDIR
   term FFCLK port IQC end
   term FFCLR port IQR end
   term FFEN port IQE end
   term P port IP end
   term FFQ port IQQ end
   term Q port IZ end
   term VCC port ESEL port OSEL port EQE end
   term GND port OQI port IE end
 end
 gate outpad_25um cell BIDIR
   term A port OQI end
   term P port IP end
   term VCC port ESEL port IE port OSEL port EQE end
   term GND port IQE port IQR port IQC end
 end
 gate ckpad_25um cell CLOCK
   term P port IP end
   term Q port IC end
 end
 gate bipadiff_25um cell BIDIR
   term A2 port OQI end
   term EN port IE end
   term FFCLK port IQC end
   term FFCLR port IQR end
   term FFEN port IQE end
   term FFQ port IQQ end
   term Q port IZ end
   term P port IP end
   term VCC port ESEL port OSEL port EQE end
 end
 gate gclkbuff_25um cell HSCKMUX
   term A port IC end
   term Z port IZ end
   term VCC port IS end
 end
 gate tripad_25um cell BIDIR
   term A port OQI end
   term EN port IE end
   term P port IP end
   term VCC port ESEL port OSEL port EQE end
   term GND port IQE port IQR port IQC end
 end
 gate bipad_25um cell BIDIR
   term A port OQI end
   term EN port IE end
   term Q port IZ end
   term P port IP end
   term VCC port ESEL port OSEL port EQE end
   term GND port IQE port IQR port IQC end
 end
 gate inpad_25um cell BIDIR
   term P port IP end
   term Q port IZ end
   term VCC port ESEL port OQI port OSEL port EQE end
   term GND port IQC port IQE port IQR port IE end
 end
 gate mux4x0 cell LOGIC
   term A port B1 end
   term B port C1 end
   term C port D1 end
   term D port E1 end
   term S0 port F1 end
   term S1 port A1 end
   term Q port OZ end
   term VCC port A5 port F3 port F5 port A3 end
   term GND port A4 port A6 port F2 port F4 port F6 port B2 port C2 port D2 port E2 port A2 end
 end
end
logical QDIF
  gates 2222
  nets 2720
  # instances
  gate I248 master pci32_25um end
  gate Rdy_Mux master mux4x0 end
  gate Mux_Data[31] master mux4x0 end
  gate Mux_Data[30] master mux4x0 end
  gate Mux_Data[29] master mux4x0 end
  gate Mux_Data[28] master mux4x0 end
  gate Mux_Data[27] master mux4x0 end
  gate Mux_Data[26] master mux4x0 end
  gate Mux_Data[25] master mux4x0 end
  gate Mux_Data[24] master mux4x0 end
  gate Mux_Data[23] master mux4x0 end
  gate Mux_Data[22] master mux4x0 end
  gate Mux_Data[21] master mux4x0 end
  gate Mux_Data[20] master mux4x0 end
  gate Mux_Data[19] master mux4x0 end
  gate Mux_Data[18] master mux4x0 end
  gate Mux_Data[17] master mux4x0 end
  gate Mux_Data[16] master mux4x0 end
  gate Mux_Data[15] master mux4x0 end
  gate Mux_Data[14] master mux4x0 end
  gate Mux_Data[13] master mux4x0 end
  gate Mux_Data[12] master mux4x0 end
  gate Mux_Data[11] master mux4x0 end
  gate Mux_Data[10] master mux4x0 end
  gate Mux_Data[9] master mux4x0 end
  gate Mux_Data[8] master mux4x0 end
  gate Mux_Data[7] master mux4x0 end
  gate Mux_Data[6] master mux4x0 end
  gate Mux_Data[5] master mux4x0 end
  gate Mux_Data[4] master mux4x0 end
  gate Mux_Data[3] master mux4x0 end
  gate Mux_Data[2] master mux4x0 end
  gate Mux_Data[1] master mux4x0 end
  gate Mux_Data[0] master mux4x0 end
  gate I228 master inpad_25um end
  gate I234 master inpad_25um end
  gate I235 master inpad_25um end
  gate I236 master inpad_25um end
  gate I237 master inpad_25um end
  gate inpad_bvd[2] master inpad_25um end
  gate inpad_bvd[1] master inpad_25um end
  gate I239 master inpad_25um end
  gate I240 master inpad_25um end
  gate I233 master inpad_25um end
  gate CIS_data[31] master inpad_25um end
  gate CIS_data[30] master inpad_25um end
  gate CIS_data[29] master inpad_25um end
  gate CIS_data[28] master inpad_25um end
  gate CIS_data[27] master inpad_25um end
  gate CIS_data[26] master inpad_25um end
  gate CIS_data[25] master inpad_25um end
  gate CIS_data[24] master inpad_25um end
  gate CIS_data[23] master inpad_25um end
  gate CIS_data[22] master inpad_25um end
  gate CIS_data[21] master inpad_25um end
  gate CIS_data[20] master inpad_25um end