ct_target.tf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

//------------------------------------------------------------------------------
//
// File : ct_target.tf
// Last Modification: May/07/2002
//
// Created In SpDE Version: SpDE 9.3
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	PCI target tests of the PCI compliance test suite.
//	 
// Hierarchy:
//	This file is to be included by pci5632_484.tf.
//
// History:	
//	Date	        Author					Version
//	06/26/01	Richard Yuan				1.0
//		- Header added to conform to coding standard.
//      May/072002      Bernhard Andretzky			1.1
//		- modified for 5632 (Device ID changed to 0x23) 	
//
//------------------------------------------------------------------------------


repeat (5) @(posedge CLK);
$display("Enabling Memory (no Mastering): %0x, time: %0t",32'h62,$time);
master_2.target_access(32'h4,32'h162,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 

target_1.IA_ENABLE = 1'b0;
repeat (5) @(posedge CLK);
$display("Interrupt Acknowledge Test: Target should NOT respond, %0d", $time);
Master_Abort_Detected = 1;
master_2.target_access(32'h22000110,64'h0,INTERRUPT_ACK,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");
target_1.IA_ENABLE = 1'b1;


repeat (5) @(posedge CLK);
$display("Special Cycle Test: Target should NOT respond, %0d", $time);
master_2.target_access(32'h22000110,64'h0,SPECIAL_CYCLE,8'hFF,1'b1,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");


repeat (5) @(posedge CLK);
$display("Special Cycle Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h22000110,64'h0,SPECIAL_CYCLE,8'hFF,1'b1,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** FAILED ***");


repeat (5) @(posedge CLK);
$display("Special Cycle Data Parity Error Test: Target should *not* assert SERRN, %0d", $time);
master_2.generate_bad_parity(3);
master_2.target_access(32'h22000110,64'h0,SPECIAL_CYCLE,8'hFF,1'b0,1'b1,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... *** Failed ***");
	SERR_Detected = 0;
	end
else $display("\t...Passed");


repeat (5) @(posedge CLK);
$display("Set the Special Cycle Enable bit, %0d", $time);
master_2.target_access(32'h4,32'h6A,CONFIG_WRITE,8'hF1,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
Master_Abort_Detected = 1;
repeat (5) @(posedge CLK);
$display("Special Cycle Data Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(3);
master_2.target_access(32'h22000110,64'h0,SPECIAL_CYCLE,8'hFF,1'b0,1'b1,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t...Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");
repeat (5) @(posedge CLK);
$display("Clear the Special Cycle Enable bit");
master_2.target_access(32'h4,32'h62,CONFIG_WRITE,8'hF1,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
Master_Abort_Detected = 1;


repeat (5) @(posedge CLK);
$display("PCI Reserved Command #1 Test: Target should NOT respond, %0d", $time);
master_2.target_access(32'h22000110,64'h0,CMD_RESERVED_1,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");


repeat (5) @(posedge CLK);
$display("PCI Reserved Command #2 Test: Target should NOT respond, %0d", $time);
master_2.target_access(32'h22000110,64'h0,CMD_RESERVED_2,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");


repeat (5) @(posedge CLK);
$display("PCI Reserved Command #3 Test: Target should NOT respond, %0d", $time);
master_2.target_access(32'h22000110,64'h0,CMD_RESERVED_3,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");


repeat (5) @(posedge CLK);
$display("PCI Reserved Command #4 Test: Target should NOT respond, %0d", $time);
master_2.target_access(32'h22000110,64'h0,CMD_RESERVED_4,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");


repeat (5) @(posedge CLK);
$display("PCI Dual Address Cycle Test: 32-bit Target should NOT respond, %0d", $time);
master_2.target_access(64'hF300000022000110,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b1); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");

$display("PCI Configuration Write and Read Test, %0d\n", $time);

$display ("Configure Target for 7 wait states, and to Stop on the 4th transfer\n");
	repeat (5) @(posedge CLK);
	master_2.target_access_pf(32'h22000118,32'h00470000,MEM_WRITE,8'hFF,1'b0,1'b0,1,2,3,1'b0, pass, 1'b0); 

$display("PCI Configuration Write and Read Test, %0d", $time);

for (i = 0; i < 16; i = i + 1) begin
	master_2.data_array[i] = 32'hFFFFFFFF;
	master_2.be_array[i] = 4'hF;
	end

$display ("Config Write Type 0: Target should respond, %0d", $time);
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h0,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display ("Config Write Type 1: Target should NOT respond, %0d", $time);
master_2.target_access_pf(32'h1,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");

repeat (5) @(posedge CLK);
$display ("Config Write Type X2: Target should NOT respond, %0d", $time);
master_2.target_access_pf(32'h2,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");

repeat (5) @(posedge CLK);
$display ("Config Write Type X3: Target should NOT respond, %0d", $time);
master_2.target_access_pf(32'h3,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");


$display ("Configure Target for normal waits, 6 retrys\n");
	repeat (5) @(posedge CLK);
	master_2.target_access_pf(32'hFFFFFD18,32'h06000000,MEM_WRITE,8'hFF,1'b0,1'b0,1,2,3,1'b0, pass, 1'b0); 


master_2.data_array[0] = 32'h001E11e3; // Device ID/ Vendor ID
master_2.data_array[1] = 32'h0280015E;
master_2.data_array[2] = 32'hFF000000;
master_2.data_array[3] = 32'h0000FFFC;
master_2.data_array[4] = 32'hFFFFFC00;
master_2.data_array[5] = 32'h00000000;
master_2.data_array[6] = 32'h00000000;
master_2.data_array[7] = 32'h00000000;
master_2.data_array[8] = 32'h00000000;
master_2.data_array[9] = 32'hFFFFFC00;		// DS added for CardBus CIS
master_2.data_array[10] = 32'h00000006;		// DS added for CardBus CIS
master_2.data_array[11] = 32'h000211e3;
master_2.data_array[12] = 32'h00000000;
master_2.data_array[13] = 32'h00000000;
master_2.data_array[14] = 32'h00000000;
master_2.data_array[15] = 32'h10080000;

repeat (5) @(posedge CLK);
$display ("Config Read Type 0: Target should respond, %0d", $time);
master_2.target_access_pf(32'h0,32'h0,CONFIG_READ,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display ("Config Read Type 1: Target should NOT respond, %0d", $time);
master_2.target_access_pf(32'h1,32'h0,CONFIG_READ,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");

repeat (5) @(posedge CLK);
$display ("Config Read Type X2: Target should NOT respond, %0d", $time);
master_2.target_access_pf(32'h2,32'h0,CONFIG_READ,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");

repeat (5) @(posedge CLK);
$display ("Config Read Type X3: Target should NOT respond, %0d", $time);
master_2.target_access_pf(32'h3,32'h0,CONFIG_READ,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... *** Failed ***");
	Master_Abort_Detected = 1;
	end
else $display("\t...Passed");

for (i = 0; i < 16; i = i + 1) begin
	master_2.data_array[i] = 32'h00000000;
	if (i == 0) master_2.be_array[i] = 4'b1000;
	else case(master_2.be_array[i-1])
		4'b0001 : master_2.be_array[i] = 4'b0010;
		4'b0010 : master_2.be_array[i] = 4'b0100;
		4'b0100 : master_2.be_array[i] = 4'b1000;
		4'b1000 : master_2.be_array[i] = 4'b0001;
		endcase
	end

$display ("Config Write Type 0 (Byte Enable Test): Target should respond, %0d", $time);
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h0,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'h001E11e3;	// Device ID/ Vendor ID
master_2.data_array[1] = 32'h02800100;
master_2.data_array[2] = 32'hFF000000;
master_2.data_array[3] = 32'h0000FFFC;
master_2.data_array[4] = 32'h00FFFC00;
master_2.data_array[5] = 32'h00000000;
master_2.data_array[6] = 32'h00000000;
master_2.data_array[7] = 32'h00000000;
master_2.data_array[8] = 32'h00000000;
master_2.data_array[9] = 32'hFFFFFC00;		// DS added for CardBus CIS
master_2.data_array[10] = 32'h00000006;		// DS added for CardBus CIS
master_2.data_array[11] = 32'h000211e3;
master_2.data_array[12] = 32'h00000000;
master_2.data_array[13] = 32'h00000000;
master_2.data_array[14] = 32'h00000000;
master_2.data_array[15] = 32'h10080000;

for (i = 0; i < 16; i = i + 1) begin
	master_2.be_array[i] = 4'hF;
	end

repeat (5) @(posedge CLK);
$display ("Config Read Type 0 (Byte Enable Test): Target should respond, %0d", $time);
master_2.target_access_pf(32'h0,32'h0,CONFIG_READ,8'hFF,1'b0,1'b0,16,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'h001011e3;
master_2.data_array[1] = 32'h0280016A;
master_2.data_array[2] = 32'hFF000001;
master_2.data_array[3] = 32'h00004000;
master_2.data_array[4] = 32'h22000000;
master_2.data_array[5] = 32'hFFFFFFFF;	// DS added for CardBus CIS
master_2.data_array[6] = 32'hFFFFFFFF;	// DS added for CardBus CIS
master_2.data_array[7] = 32'hFFFFFFFF;	// DS added for CardBus CIS
master_2.data_array[8] = 32'hFFFFFFFF;	// DS added for CardBus CIS
master_2.data_array[9] = 32'hCB000000;	// DS added for CardBus CIS

repeat (5) @(posedge CLK);
$display ("Resetting the Device for Configuration Read/Write Parity Error Test, %0d", $time);
master_2.target_access_pf(32'h0,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,10,2,3,1'b0, pass, 1'b0); 	// DS was 5, now 10
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'h22000000;
master_2.data_array[1] = 32'h0280016A;
master_2.data_array[2] = 32'hFF000001;
for (i = 0; i < 3; i = i + 1)
	master_2.be_array[i] = 4'hF;

repeat (5) @(posedge CLK);
$display("Configuration Read Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h00000004,64'h0,CONFIG_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Configuration Write Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h00000010,32'h22000000,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Configuration Write Data (Phase 1) Parity Error Test: Target should assert PERRN, %0d", $time);
PERR_Detected = 0;
master_2.generate_bad_parity(3);
master_2.target_access(32'h00000010,64'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h03,4'h1,4'h1,1'b0); 
if (PERR_Detected) begin
	$display("\t... Passed");
	PERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

$display("Configuration Write Data (Phase 2) Parity Error Test: Target should assert PERRN, %0d", $time);
	repeat (5) @(posedge CLK);
	master_2.generate_bad_parity(5);
	master_2.target_access(32'h00000010,64'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,7'h03,4'h1,4'h1,1'b0); 
	if (PERR_Detected) begin